
LIST OF FIGURES
vi
EPSON
S1C38000 TECHNICAL MANUAL
Figure 6-35
Single Monochrome 4-Bit Panel Timing.............................................................................62
Figure 6-36
Single Monochrome 4-Bit Panel A.C. Timing.....................................................................63
Figure 6-37
Single Monochrome 8-Bit Panel Timing.............................................................................64
Figure 6-38
Single Monochrome 8-Bit Panel A.C. Timing.....................................................................65
Figure 6-39
Single Color 4-Bit Panel Timing .........................................................................................66
Figure 6-40
Single Color 4-Bit Panel A.C. Timing .................................................................................67
Figure 6-41
Single Color 8-Bit Panel Timing (Format 1) .......................................................................68
Figure 6-42
Single Color 8-Bit Panel A.C. Timing (Format 1) ...............................................................69
Figure 6-43
Single Color 8-Bit Panel Timing (Format 2) .......................................................................70
Figure 6-44
Single Color 8-Bit Panel A.C. Timing (Format 2) ...............................................................71
Figure 6-45
Single Color 16-Bit Panel Timing .......................................................................................72
Figure 6-46
Single Color 16-Bit Panel A.C. Timing ...............................................................................73
Figure 6-47
Generic TFT Panel Timing .................................................................................................74
Figure 6-48
18-Bit TFT Panel Timing ....................................................................................................75
Figure 6-49
TFT A.C. Timing.................................................................................................................76
Figure 6-50
160x160 Sharp ‘Direct’ HR-TFT Panel Horizontal Timing .................................................77
Figure 6-51
160x160 Sharp ‘Direct’ HR-TFT Panel Vertical Timing......................................................78
Figure 6-52
320x240 Sharp ‘Direct’ HR-TFT Panel Horizontal Timing .................................................79
Figure 6-53
320x240 Sharp ‘Direct’ HR-TFT Panel Vertical Timing......................................................80
Figure 7-1
Internal Architecture Block Diagram ..................................................................................81
Figure 8-1
ARM720T and AHB Wrapper Block Diagram ....................................................................91
Figure 11-1
Routing Paths of Internal Clocks........................................................................................99
Figure 11-2
Clocking Mode and Power Down Mode Transition Diagram ............................................101
Figure 15-1
LCDC Functional Block Diagram ......................................................................................118
Figure 15-2
Clock Selection .................................................................................................................120
Figure 15-3
Display Data Byte/Word Swap ..........................................................................................134
Figure 15-4
PWM Clock/CV Pulse Block Diagram ...............................................................................135
Figure 15-5
4/8/16 Bit-Per-Pixel Display Data Memory Organization ..................................................140
Figure 15-6
1 Bit-Per-Pixel Monochrome Mode Data Output Path ......................................................141
Figure 15-7
2 Bit-Per-Pixel Monochrome Mode Data Output Path ......................................................141
Figure 15-8
4 Bit-Per-Pixel Monochrome Mode Data Output Path ......................................................141
Figure 15-9
8 Bit-Per-Pixel Monochrome Mode Data Output Path ......................................................142
Figure 15-10 1 Bit-Per-Pixel Color Mode Data Output Path...................................................................143
Figure 15-11 2 Bit-Per-Pixel Color Mode Data Output Path...................................................................144
Figure 15-12 4 Bit-Per-Pixel Color Mode Data Output Path...................................................................145
Figure 15-13 8 Bit-Per-Pixel Color Mode Data Output Path...................................................................146
Figure 15-14 Relationship between the Screen Image and the Image Refreshed in 90° SwivelView.....148
Figure 15-15 Relationship between the Screen Image and the Image Refreshed in 180° SwivelView...149
Figure 15-16 Relationship between the Screen Image and the Image Refreshed in 270° SwivelView...150
Figure 15-17 Picture-in-Picture Plus with SwivelView Disabled .............................................................151
Figure 15-18 Picture-in-Picture Plus with SwivelView 90° Enabled .......................................................151
Figure 15-19 Picture-in-Picture Plus with SwivelView 180° Enabled .....................................................152
Figure 15-20 Picture-in-Picture Plus with SwivelView 270° Enabled .....................................................152
Figure 15-21 Byte-swapping for 16 Bpp .................................................................................................153
Figure 15-22 Byte-swapping for 1/2/4/8 Bpp ..........................................................................................154
Figure 21-1
SIR Mode ..........................................................................................................................202
Figure 21-2
FIR Mode ..........................................................................................................................203
Figure 22-1
Functional Flow in Master Mode for SPI1 .........................................................................205
Figure 22-2
Functional Flow in Slave Mode for SPI1 ...........................................................................205
Figure 22-3
SPI1 Block Diagram ..........................................................................................................206