
RCPU
REFERENCE MANUAL
ADDRESSING MODES AND INSTRUCTION SET SUMMARY
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MOTOROLA
4-3
4.2 Classes of Instructions
PowerPC instructions belong to one of three classes:
Defined
Illegal
Reserved
Note that while the definitions of these terms are consistent among the PowerPC
processors, the assignment of these classifications is not. For example, an instruc-
tion that is specific to 64-bit implementations is considered defined for 64-bit imple-
mentations but illegal for 32-bit implementations such as the RCPU.
The class is determined by examining the primary opcode and the extended op-
code, if any. If the opcode, or combination of opcode and extended opcode, is not
that of a defined instruction or a reserved instruction, the instruction is illegal.
In future versions of the PowerPC architecture, instruction codings that are now il-
legal may become defined (by being added to the architecture) or reserved (by be-
ing assigned to one of the special purposes). Likewise, reserved instructions may
become defined.
4.2.1 Definition of Boundedly Undefined
The results of executing a given instruction are said to be boundedly undefined if
they could have been achieved by executing an arbitrary sequence of instructions,
starting in the state the machine was in before executing the given instruction.
Boundedly undefined results for a given instruction may vary between implemen-
tations and between execution attempts on the same implementation.
4.2.2 Defined Instruction Class
Defined instructions include all the instructions defined in the PowerPC UISA, VEA,
and OEA. Defined instructions can be required or optional. The RCPU supports the
following defined instructions:
All 32-bit PowerPC UISA required instructions
The following PowerPC VEA instructions:
eieio
,
icbi
,
isync
, and
mftb
The following PowerPC OEA instructions:
mfmsr
,
mfspr
,
mtmsr
,
mtspr
,
rfi
,
and
sc
.
The following optional instruction:
stfiwx
A defined instruction may have an instruction form that is invalid if one or more op-
erands, excluding opcodes, are coded incorrectly in a manner that can be deduced
by examining only the instruction encoding (primary and extended opcodes). For
example, an invalid form results when a reserved bit (shown as “0” in the instruction
descriptions in
SECTION 9 INSTRUCTION SET
) is set to one.
Attempting to execute an invalid form of a defined instruction either invokes the
software emulation instruction error handler or yields boundedly undefined results.
Where not otherwise noted in the individual instruction descriptions in
SECTION 9
INSTRUCTION SET
for individual instruction descriptions, attempting to execute
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n
.