
RCPU
REFERENCE MANUAL
EXCEPTIONS
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MOTOROLA
6-29
6.11.7 Decrementer Exception (0x00900)
A decrementer exception occurs when no higher priority exception exists, the dec-
rementer register has completed decrementing, and MSR[EE] = 1. The decrement-
er exception request is canceled when the exception is handled. The decrementer
register counts down, causing an exception (unless masked) when passing
through zero. The decrementer implementation meets the following requirements:
Loading a GPR from the decrementer does not affect the decrementer.
Storing a GPR value to the decrementer replaces the value in the decrementer
with the value in the GPR.
Whenever bit 0 of the decrementer changes from zero to one, an exception
request is signaled. If multiple decrementer exception requests are received
before the first can be reported, only one exception is reported. The occur-
rence of a decrementer exception cancels the request.
If the decrementer is altered by software and if bit 0 is changed from zero to
one, an interrupt request is signaled.
The register settings for the decrementer exception are shown in
Table 6-20
.
When a decrementer exception is taken, instruction execution resumes at offset
0x00900 from the physical base address indicated by MSR[IP].
6.11.8 System Call Exception (0x00C00)
A system call exception occurs when a system call instruction is executed. The ef-
fective address of the instruction following the
sc
instruction is placed into SRR0.
MSR[16:31] are placed into SRR1[16:31], and SRR1[0:15] are set to undefined
values. Then a system call exception is generated.
The system call instruction is context synchronizing. That is, when a system call
exception occurs, instruction dispatch is halted and the following synchronization
is performed:
1. The exception mechanism waits for all instructions in execution to complete
to a point where they report all exceptions they will cause.
2. The processor ensures that all instructions in execution complete in the con-
Table 6-20 Register Settings Following a Decrementer Exception
Register
Setting Description
SRR0
Set to the effective address of the instruction that the processor would have attempted to execute next
if no exception conditions were present.
SRR1
[0:15]
[16:31]
Cleared
Loaded from MSR[16:31]
MSR
IP
ME
LE
Other bits
No change
No change
Set to value of ILE bit prior to the exception
Cleared to zero
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