
MOTOROLA
4-24
ADDRESSING MODES AND INSTRUCTION SET SUMMARY
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RCPU
REFERENCE MANUAL
Floating-
Point
Negative
Multiply-
Add
fnmadd
fnmadd.
fr
D
,fr
A
,fr
C
,fr
B
The floating-point operand in register
fr
A is multiplied by the floating-
point operand in register
fr
C. The floating-point operand in register
fr
B
is added to this intermediate result.
If the most significant bit of the resultant significand is not a one the
result is normalized. The result is rounded to the target precision
under control of the floating-point rounding control field RN of the
FPSCR, then negated and placed into register
fr
D.
This instruction produces the same result as would be obtained by
using the floating-point multiply-add instruction and then negating the
result, with the following exceptions:
QNaNs propagate with no effect on their sign bit.
QNaNs that are generated as the result of a disabled invalid
operation exception have a sign bit of zero.
SNaNs that are converted to QNaNs as the result of a disabled
invalid operation exception retain the sign bit of the SNaN.
FPSCR[FPRF] is set to the class and sign of the result, except for
invalid operation exceptions when FPSCR[VE] = 1.
fnmadd
fnmadd.
Floating-Point Negative Multiply-Add
Floating-Point Negative Multiply-Add with CR Update.
The dot suffix enables the update of the condition
register.
Floating-
Point
Negative
Multiply-
Add
Single-
Precision
fnmadds
fnmadds.
fr
D
,fr
A
,fr
C
,fr
B
The floating-point operand in register
fr
A is multiplied by the floating-
point operand in register
fr
C. The floating-point operand in register
fr
B
is added to this intermediate result.
If the most significant bit of the resultant significand is not a one the
result is normalized. The result is rounded to the target precision
under control of the floating-point rounding control field RN of the
FPSCR, then negated and placed into register
fr
D.
This instruction produces the same result as would be obtained by
using the floating-point multiply-add instruction and then negating the
result, with the following exceptions:
QNaNs propagate with no effect on their sign bit.
QNaNs that are generated as the result of a disabled invalid
operation exception have a sign bit of zero.
SNaNs that are converted to QNaNs as the result of a disabled
invalid operation exception retain the sign bit of the SNaN.
FPSCR[FPRF] is set to the class and sign of the result, except for
invalid operation exceptions when FPSCR[VE] = 1.
fnmadds
fnmadds.
Floating-Point Negative Multiply-Add Single-Precision
Floating-Point Negative Multiply-Add Single-Precision
with CR Update. The dot suffix enables the update of the
condition register.
Table 4-8 Floating-Point Multiply-Add Instructions (Continued)
Name
Mnemonic
Operand
Syntax
Operation
F
Freescale Semiconductor, Inc.
n
.