
RCPU
REFERENCE MANUAL
DEVELOPMENT SUPPORT
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MOTOROLA
8-35
transmission, a sequencing error is shifted out of the development port, and the
data shifted into the shift register is thrown away. During the third transmission, the
“CPU exception” status is output, and again the data shifted into the shift register
is thrown away. During the fourth transmission, an instruction is again shifted into
the development port and fetched by the CPU for execution. Notice in this example
that the development port throws away the first two input transmissions following
the one causing the sequencing error.
8.3.8.3 CPU Exception Output
The
CPU exception
encoding is used to indicate that the CPU encountered an ex-
ception during the execution of the previous instruction in debug mode. Exceptions
may occur as the result of instruction execution (such as unimplemented opcode
or arithmetic error), because of a memory access fault, or from an external inter-
rupt. The exception is recognized only if the associated bit in the DER is set. When
an exception occurs, the development port ignores the data being shifted in while
the CPU exception status is shifting out. The port terminates the current CPU ac-
cess with a bus error. The next transmission to the port should be a new instruction
or trap enable data.
8.3.8.4 Null Output
Finally, the
null
encoding is used to indicate that no data has been transferred from
the CPU to the development port shift register. It also indicates that the previous
transmission did not have any associated errors.
8.3.9 Use of the Ready Bit
To minimize the overhead required to detect and correct errors, the external devel-
opment system should wait for the ready bit on DSDO before beginning each input
transmission. This ensures that all CPU activity (if any) relative to the previous
transmission has been completed and that any errors have been reported.
Table 8-16 Sequencing Error Activity
Trans #
Input to
Development
Port
Output from
Development
Port
Port Action
CPU Action
1
CPU Data
(Control bit = 1)
Depends on
previous
transmissions
Cause bus error, set
sequence error latch
Fetch instruction, take
exception because of bus
error
2
X (Thrown away)
Sequencing Error
Set exception latch, clear
sequencing error latch
Signal exception to port,
begin new fetch from port
3
X (Thrown away)
CPU Exception
Clear exception latch
Continue to wait for
instruction from port
4
CPU instruction
Null
Send instruction to CPU
at end of transmission
Fetch instruction from port
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