
Table
Title
Page
RCPU
REFERENCE MANUAL
LIST OF TABLES
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MOTOROLA
xvii
6-11 Exception Latency ............................................................................................. 6-19
6-12 Settings Caused by Reset................................................................................ 6-20
6-13 Machine Check Exception Processor Actions................................................... 6-21
6-14 Register Settings Following a Machine Check Exception................................. 6-22
6-15 Register Settings Following External Interrupt.................................................. 6-23
6-16 Register Settings for Alignment Exception ....................................................... 6-24
6-17 DSISR[15:21] Settings...................................................................................... 6-25
6-18 Register Settings Following Program Exception............................................... 6-28
6-19 Register Settings Following a Floating-Point Unavailable Exception ............... 6-28
6-20 Register Settings Following a Decrementer Exception..................................... 6-29
6-21 Register Settings Following a System Call Exception...................................... 6-30
6-22 Register Settings Following a Trace Exception................................................ 6-30
6-23 Register Settings Following a Floating-Point Assist Exception......................... 6-31
6-24 Software/Hardware Partitioning in Operands Treatment................................... 6-33
6-25 FPECR Bit Settings .......................................................................................... 6-35
6-26 FPSCR Bit Settings .......................................................................................... 6-36
6-27 Floating-Point Result Flags in FPSCR.............................................................. 6-38
6-28 Floating-Point Exception Mode Bits.................................................................. 6-41
6-29 Register Settings Following a Software Emulation Exception.......................... 6-47
6-30 Register Settings Following Data Breakpoint Exception................................... 6-48
6-31 Register Settings Following an Instruction Breakpoint Exception..................... 6-48
6-32 Register Settings Following a
Maskable External Breakpoint Exception...................................................... 6-49
6-33 Register Settings Following a
Non-Maskable External Breakpoint Exception.............................................. 6-50
7-1 Load/Store Instructions Timing............................................................................. 7-8
7-2 Encodings of External-to-the-Processor SPRs.................................................... 7-11
7-3 Instruction Execution Timing................................................................................ 7-12
7-4 Control Registers and Serialized Access............................................................. 7-15
8-1 Program Trace Cycle Attribute Encodings............................................................. 8-3
8-2 Fetch Show Cycles Control ................................................................................... 8-4
8-3 VF Pins Instruction Encodings.............................................................................. 8-5
8-4 VF Pins Queue Flush Encodings........................................................................... 8-6
8-5 VFLS Pin Encodings.............................................................................................. 8-6
8-6 Cycle Type Encodings........................................................................................... 8-7
8-7 Detecting the Trace Buffer Starting Point............................................................ 8-10
8-8 I-bus Watchpoint Programming Options.............................................................. 8-17
8-9 L-Bus Data Events............................................................................................... 8-19
8-10 L-Bus Watchpoints Programming Options......................................................... 8-19
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