
Figure
Title
Page
MOTOROLA
xiv
LIST OF FIGURES
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RCPU
REFERENCE MANUAL
4-9
4-10
4-11
Branch Conditional to Absolute Addressing ................................................. 4-52
Branch Conditional to Link Register Addressing .......................................... 4-53
Branch Conditional to Count Register Addressing ....................................... 4-54
5-1
5-2
Instruction Cache Organization ...................................................................... 5-2
Instruction Cache Data Path ........................................................................... 5-3
6-1
6-2
6-3
History Buffer Queue ...................................................................................... 6-8
RCPU Floating-Point Architecture ................................................................ 6-32
Real Numbers Axis for Denormalized Operands .......................................... 6-33
7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
7-9
7-10
7-11
7-12
7-13
Instruction Flow .............................................................................................. 7-2
Instruction Sequencer Data Path .................................................................... 7-3
Basic Instruction Pipeline ............................................................................... 7-5
Number of Bus Cycles Needed for String Instruction Execution .................... 7-8
Load from Internal Memory Example ........................................................... 7-17
Write-Back Arbitration Example I .................................................................. 7-17
Write-Back Arbitration Example II ................................................................. 7-18
Load with Private Write-Back Bus Example ................................................. 7-19
External Load Example ................................................................................ 7-20
History Buffer Full Example .......................................................................... 7-21
Store and Floating-Point Example ................................................................ 7-22
Branch Folding Example .............................................................................. 7-23
Branch Prediction Example .......................................................................... 7-24
8-1
8-2
8-3
8-4
8-5
8-6
8-7
8-8
8-9
8-10
8-11
8-12
8-13
8-14
Watchpoint and Breakpoint Support in the RCPU ........................................ 8-12
Partially Supported Watchpoint/Breakpoint Example ................................... 8-15
I-Bus Support General Structure .................................................................. 8-16
L-Bus Support General Structure ................................................................. 8-18
Development Port Support Logic .................................................................. 8-23
Development Port Registers and Data Paths ............................................... 8-25
Enabling Clock Mode Following Reset ......................................................... 8-28
Asynchronous Clocked Serial Communications ........................................... 8-29
Synchronous Clocked Serial Communications ............................................. 8-30
Synchronous Self-Clocked Serial Communications ..................................... 8-31
Enabling Debug Mode at Reset .................................................................... 8-37
Entering Debug Mode Following Reset ........................................................ 8-38
General Port Usage Sequence Diagram ...................................................... 8-43
Debug Mode Logic ....................................................................................... 8-47
9-1
Instruction Description .................................................................................... 9-6
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