
MOTOROLA
2-12
REGISTERS
RCPU
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REFERENCE MANUAL
2.2.7 Count Register (CTR)
The count register (CTR) is a 32-bit register for holding a loop count that can be
decremented during execution of branch instructions that contain an appropriately
coded BO field. If the value in CTR is zero before being decremented, it is negative
one afterward. The count register provides the branch target address for the
branch conditional to count register (
bcctr
x
) instruction.
Prefetching instructions along the target path is also possible provided the count
register is loaded sufficiently ahead of the branch instruction.
The count register can be accessed by the
mtspr
and
mfspr
instructions by spec-
ifying SPR 9. In branch conditional instructions, the BO field specifies the condi-
tions under which the branch is taken. The first four bits of the BO field specify how
the branch is affected by or affects the condition register and the count register.
The encoding for the BO field is shown in
Table 4-21
in
SECTION 4 ADDRESSING
MODES AND INSTRUCTION SET SUMMARY
.
2.3 PowerPC VEA Register Set — Time Base
The PowerPC virtual environment architecture (VEA) defines registers in addition
to those in the UISA register set. The PowerPC VEA register set can be accessed
by all software with either user- or supervisor-level privileges.
The PowerPC VEA includes the time base facility (TB), a 64-bit structure that con-
tains a 64-bit unsigned integer that is incremented periodically. The frequency at
which the counter is updated is implementation-dependent and need not be con-
stant over long periods of time.
The TB consists of two 32-bit registers: time base upper (TBU) and time base lower
(TBL). In the context of the VEA, user-level applications are permitted read-only ac-
cess to the TB. The OEA defines supervisor-level access to the TB for writing val-
ues to the TB. Different SPR encodings are provided for reading and writing the
time base.
Refer to
2.4 PowerPC OEA Register Set
for more information on writing to the TB.
Refer to
4.7.2 Move to/from Special Purpose Register Instructions
for simpli-
fied mnemonics for reading and writing to the time base. For information on the
time base clock source, refer to the
System Interface Unit Reference Manual (SI-
URM/AD)
.
CTR
— Count Register
SPR 9
0
31
Loop Count
RESET: UNCHANGED
F
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n
.