
RCPU
REFERENCE MANUAL
ADDRESSING MODES AND INSTRUCTION SET SUMMARY
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MOTOROLA
4-63
Table 4-31
summarizes SPR encodings that the RCPU permits in debug mode, or
in supervisor mode when debug mode is not enabled out of reset.
Table 4-30 Supervisor-Level SPR Encodings
Decimal
Value in rD
1
NOTES:
1. If the SPR field contains any value other than one of the values shown in
Table 4-30
, the instruction form
is invalid. For an invalid instruction form in which SPR[0]=1, either a privileged instruction type program ex-
ception or software emulation exception is generated if the instruction is executed by a user-level program.
(Refer to the discussion of these two exception types in
SECTION 6 EXCEPTIONS
for more information.)
If the instruction is executed by a supervisor-level program, the software emulation exception handler is in-
voked.
SPR[0] = 1 if and only if writing the register is supervisor-level. Execution of this instruction specifying a
defined and supervisor-level register when MSR[PR] = 1 results in a privileged instruction type program ex-
ception.
2. The PowerPC architecture defines the encodings as TBRs, although it is the same as the SPR encodings.
Moving to the time base is performed by the
mtspr
instruction, and moving from the time base is performed
by the
mftb
instruction.
SPR[0:4
]
SPR[5:9]
Register
Name
Description
18
0b10010 00000
DSISR
DAE/source instruction service register
19
0b10011 00000
DAR
Data address register
22
0b10110 00000
DEC
Decrementer register
26
0b11010 00000
SRR0
Save and restore register 0
27
0b11011 00000
SRR1
Save and restore register 1
80
0b10000 00010
EIE
External interrupt enable (write only)
81
0b10001 00010
EID
External interrupt disable (write only)
82
0b10010 00010
NRI
Non-recoverable exception
272
0b10000 01000
SPRG0
SPR general 0
273
0b10001 01000
SPRG1
SPR general 1
274
0b10010 01000
SPRG2
SPR general 2
275
0b10011 01000
SPRG3
SPR general 3
284
0b11100 01000
TBL
2
Time base — lower (write only)
285
0b11101 01000
TBU
2
Time base — upper (write only)
287
0b11111 01000
PVR
Processor version register (read only)
560
0b10000 10001
ICCST
I-Cache Control and Status Register
561
0b10001 10001
ICADR
I-cache address register
562
0b10010 10001
ICDAT
I-cache data port
1022
0b11110 11111
FPECR
Floating-point exception cause register
F
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