
RCPU
REFERENCE MANUAL
INSTRUCTION TIMING
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MOTOROLA
7-7
7.2.3.1 Load/Store Instruction Issue
When a load or store instruction is encountered, the LSU checks the scoreboard to
determine if all the operands are available. These operands include:
Address registers operands
Source data register operands (for store instructions)
Destination data register operands (for load instructions)
Destination address register operands (for load/store with update instructions)
If all operands are available, the LSU takes the instruction and enables the se-
quencer to issue a new instruction. Using a dedicated interface, the LSU notifies
the IU to calculate the effective address.
All load and store instructions are executed and terminated in order. If there are no
prior instructions waiting in the address queue, the load or store instruction is is-
sued to the L-bus as soon as the instruction is taken. Otherwise, if there are still
prior instructions whose address are still to be issued to the L-bus, the instruction
is inserted into the address queue, and data (for store instructions) is inserted into
the respective store data queue. Note that for load/store with update instructions,
the destination address register is written back on the following clock cycle, regard-
less of the state of the address queue.
A new store instruction is not issued to the L-bus until all prior instructions have ter-
minated without an exception. This is done in order to implement the PowerPC pre-
cise exception model. In case of a load instruction followed by a store instruction,
a delay of one clock cycle is inserted between the termination of the load bus cycle
and the issuing of the store cycle.
7.2.3.2 Load/Store Synchronizing Instructions
For certain LSU instructions, the instruction is not taken (as defined in the glossary)
until all previous instructions have terminated. These instructions are:
Load/Store Multiple instructions —
lmw
,
stmw
Storage Synchronization instructions —
lwarx
,
stwcx
,
sync
String instructions —
lswi
,
lswx
,
stswi
,
stswx
Move to internal special registers and move to external-to-processor special
purpose registers
Issuing of further instructions is stalled until the following load/store instructions ter-
minate:
Load/Store Multiple insturctions —
lmw
,
stmw
Storage Synchronization instructions —
lwarx
,
stwcx
,
sync
String instructions —
lswi
,
lswx
,
stswi
,
stswx
7.2.3.3 Load/Store Instruction Timing Summary
Table 7-1
summarizes the timing of load/store instructions, assuming a parked bus
and zero wait state memory references. The parameter “N” denotes the number of
registers transferred.
F
Freescale Semiconductor, Inc.
n
.