
MOTOROLA
4-28
ADDRESSING MODES AND INSTRUCTION SET SUMMARY
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RCPU
REFERENCE MANUAL
4.4.5 Floating-Point Status and Control Register Instructions
Every FPSCR instruction appears to synchronize the effects of all floating-point in-
structions executed by a given processor. Executing an FPSCR instruction en-
sures that all floating-point instructions previously initiated by the given processor
appear to have completed before the FPSCR instruction is initiated and that no
subsequent floating-point instructions appear to be initiated by the given processor
until the FPSCR instruction has completed. In particular:
All exceptions caused by the previously initiated instructions are recorded in
the FPSCR before the FPSCR instruction is initiated.
All invocations of the floating-point exception handler caused by the previously
initiated instructions have occurred before the FPSCR instruction is initiated.
No subsequent floating-point instruction that depends on or alters the settings
of any FPSCR bits appears to be initiated until the FPSCR instruction has
completed.
Floating-point memory access instructions are not affected.
The floating-point status and control register instructions are summarized in
Table
4-12
.
Table 4-11 Floating-Point Compare Instructions
Name
Mnemonic
Operand
Syntax
Operation
Floating-
Point
Compare
Unordered
fcmpu
crf
D
,fr
A
,fr
B
The floating-point operand in register
fr
A is compared to the floating-
point operand in register
fr
B. The result of the compare is placed into
CR field
crf
D and the FPCC.
If an operand is a NaN, either quiet or signaling, CR field
crf
D and the
FPCC are set to reflect unordered. If an operand is a Signaling NaN,
VXSNAN is set.
Floating-
Point
Compare
Ordered
fcmpo
crf
D
,fr
A
,fr
B
The floating-point operand in register
fr
A is compared to the floating-
point operand in register
fr
B. The result of the compare is placed into
CR field
crf
D and the FPCC.
If an operand is a NaN, either quiet or signaling, CR field
crf
D and the
FPCC are set to reflect unordered. If an operand is a Signaling NaN,
VXSNAN is set, and if invalid operation is disabled (VE = 0) then VXVC
is set. Otherwise, if an operand is a Quiet NaN, VXVC is set.
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.