
RCPU
REFERENCE MANUAL
EXCEPTIONS
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MOTOROLA
6-19
At time-point A the excepting instruction issues and begins execution. During the
interval A-B previously issued instructions are finishing execution. The interval A-
B is equivalent to the time required for all instructions currently in progress to com-
plete, (i.e., the time to serialize the machine).
At time-point B the excepting instruction has reached the head of the history queue,
implying that all instructions preceding it in the code stream have finished execu-
tion without generating any exception. In addition, the excepting instruction itself
has completed execution. At this time the exception is recognized, and exception
processing begins. If at this point the instruction had not generated an exception,
it would have been retired.
During the interval B-D the machine state is being restored. This can take up to
three clock cycles.
At time-point C the processor starts fetching the first instruction of the exception
handler.
By time-point D the state of the machine prior to the issue of the excepting instruc-
tion has been restored. During interval D-E, the machine is saving context informa-
tion in SRR0 and SRR1, disabling interrupts, placing the machine in privileged
mode, and may continue the process of fetching the first instructions of the interrupt
handler from the vector table.
At time-point E the MSR and instruction pointer of the executing process have been
saved and control has been transferred to the exception handler routine.
The interval D-E requires a minimum of one clock cycle. The interval C-E depends
on the memory system. This interval is the time it takes to fetch the first instruction
of the exception handler. For a full history buffer, it is no less then two clocks.
Table 6-11 Exception Latency
Time
Fetch
Issue
Instruction Complete
Kill Pipeline
A
Faulting instruction
issue
B
Instruction complete and all
previous instructions
complete
Kill pipeline
C
Start fetch
handler
D
≤
B + 3 clocks
E
1st instruction of
handler issued
F
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