
RCPU
REFERENCE MANUAL
EXCEPTIONS
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MOTOROLA
6-15
Table 6-7 Machine State Register Bit Settings
Bit(s)
Name
Description
[0:14]
—
Reserved
15
ILE
Exception little-endian mode. When an exception occurs, this bit is copied into MSR[LE] to se-
lect the endian mode for the context established by the exception.
0
Processor runs in big-endian mode during exception processing.
1
Processor runs in little-endian mode during exception processing.
16
EE
External interrupt enable
0
The processor delays recognition of external interrupts and decrementer exception condi-
tions.
1
The processor is enabled to take an external interrupt or the decrementer exception.
17
PR
Privilege level
0
The processor can execute both user- and supervisor-level instructions.
1
The processor can only execute user-level instructions.
18
FP
Floating-point available
0
The processor prevents dispatch of floating-point instructions, including floating-point
loads, stores and moves. Floating-point enabled program exceptions can still occur and
the FPRs can still be accessed.
1
The processor can execute floating-point instructions, and can take floating-point enabled
exception type program exceptions.
19
ME
Machine check enable
0
Machine check exceptions are disabled.
1
Machine check exceptions are enabled.
20
FE0
Floating-point exception mode 0 (See
Table 6-8
.)
21
SE
Single-step trace enable
0
The processor executes instructions normally.
1
The processor generates a single-step trace exception upon the successful execution of
the next instruction. When this bit is set, the processor dispatches instructions in strict pro-
gram order. Successful execution means the instruction caused no other exception. Sin-
gle-step tracing may not be present on all implementations.
22
BE
Branch trace enable
23
FE1
Floating-point exception mode 1 (See
Table 6-8
.)
24
—
Reserved
25
IP
Exception prefix. The setting of this bit determines the location of the exception vector table.
0
Exceptions are vectored to the physical address 0x0000 0000 plus vector offset.
1
Exceptions are vectored to the physical address 0xFFF0 0000 plus vector offset.
[26:29]
—
Reserved
30
RI
Recoverable exception
0
Exception is not recoverable.
1
Exception is recoverable.
31
LE
Little-endian mode
0
Processor operates in big-endian mode during normal processing.
1
Processor operates in little-endian mode during normal processing.
F
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