
MOTOROLA
3-10
OPERAND CONVENTIONS
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RCPU
REFERENCE MANUAL
gram executing in little-endian mode would use to access the instructions as
data words using a load instruction.
A target address in an absolute branch instruction is the address that a pro-
gram executing in little-endian mode would use to access the target instruc-
tion as a word of data using a load instruction.
3.2.4 Input/Output in Little-Endian Mode
Input/output operations transfer a byte stream on both big- and little-endian sys-
tems. For a PowerPC system running in big-endian mode, both the processor and
the memory subsystem recognize the same byte as byte 0. However, this is not
true for a PowerPC system running in little-endian mode because of the modifica-
tion of the three low-order bits when the processor accesses memory.
In order for I/O transfers in little-endian mode to appear to transfer bytes properly,
they must be performed as if the bytes transferred were accessed one at a time,
using the little-endian address modification appropriate for the single-byte transfers
(XOR the bits with 0b111). This does not mean that I/O on little-endian PowerPC
machines must be done using only one-byte-wide transfers. Data transfers can be
as wide as desired, but the order of the bytes within double words must be as if
they were fetched or stored one at a time.
3.3 Floating-Point Data
This subsection describes how floating-point data is represented in floating-point
registers and in memory.
3.3.1 Floating-Point Data Format
The PowerPC architecture defines the representation of a floating-point value in
two different binary, fixed-length formats: a 32-bit format for a single-precision
floating-point value or a 64-bit format for a double-precision floating-point value.
Data in memory may use either the single-precision or double-precision format.
Floating-point registers use the double-precision format.
The length of the exponent and the fraction fields differ between these two preci-
sion formats. The structure of the single-precision format is shown in
Figure 3-10
;
the structure of the double-precision format is shown in
Figure 3-11
.
Figure 3-10 Floating-Point Single-Precision Format
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