
MOTOROLA
4-20
ADDRESSING MODES AND INSTRUCTION SET SUMMARY
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RCPU
REFERENCE MANUAL
Floating-
Point Add
Single-
Precision
fadds
fadds.
fr
D
,fr
A
,fr
B
The floating-point operand in register
fr
A is added to the floating-point
operand in register
fr
B. If the most significant bit of the resultant
significand is not a one, the result is normalized. The result is rounded
to the target precision under control of the floating-point rounding
control field RN of the FPSCR and placed into register
fr
D.
Floating-point addition is based on exponent comparison and addition
of the two significands. The exponents of the two operands are
compared, and the significand accompanying the smaller exponent is
shifted right, with its exponent increased by one for each bit shifted,
until the two exponents are equal. The two significands are then
added algebraically to form an intermediate sum. All 53 bits in the
significand as well as all three guard bits (G, R, and X) enter into the
computation.
If a carry occurs, the sum's significand is shifted right one bit position
and the exponent is increased by one.
FPSCR[FPRF] is set to the class and sign of the result, except for
invalid operation exceptions when FPSCR[VE] = 1.
fadds
fadds.
Floating-Point Single-Precision
Floating-Point Single-Precision with CR Update. The dot
suffix enables the update of the condition register.
Floating-
Point
Subtract
fsub
fsub.
fr
D
,fr
A
,fr
B
The floating-point operand in register
fr
B is subtracted from the
floating-point operand in register
fr
A. If the most significant bit of the
resultant significand is not a one the result is normalized. The result is
rounded to the target precision under control of the floating-point
rounding control field RN of the FPSCR and placed into register
fr
D.
The execution of the Floating-Point Subtract instruction is identical to
that of Floating-Point Add, except that the contents of register
fr
B
participates in the operation with its sign bit (bit 0) inverted.
FPSCR[FPRF] is set to the class and sign of the result, except for
invalid operation exceptions when FPSCR[VE] = 1.
fsub
fsub.
Floating-Point Subtract
Floating-Point Subtract with CR Update. The dot suffix
enables the update of the condition register.
Floating-
Point
Subtract
Single-
Precision
fsubs
fsubs.
fr
D
,fr
A
,fr
B
The floating-point operand in register
fr
B is subtracted from the
floating-point operand in register
fr
A. If the most significant bit of the
resultant significand is not a one the result is normalized. The result is
rounded to the target precision under control of the floating-point
rounding control field RN of the FPSCR and placed into register
fr
D.
The execution of the Floating-Point Subtract instruction is identical to
that of Floating-Point Add, except that the contents of register
fr
B
participates in the operation with its sign bit (bit 0) inverted.
FPSCR[FPRF] is set to the class and sign of the result, except for
invalid operation exceptions when FPSCR[VE] = 1.
fsubs
fsubs.
Floating-Point Subtract Single-Precision
Floating-Point Subtract Single-Precision with CR Update.
The dot suffix enables the update of the condition
register.
Table 4-7 Floating-Point Arithmetic Instructions (Continued)
Name
Mnemonic
Operand
Syntax
Operation
F
Freescale Semiconductor, Inc.
n
.