
MOTOROLA
6-8
EXCEPTIONS
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RCPU
REFERENCE MANUAL
Figure 6-1 History Buffer Queue
An exception can be detected at any time during instruction execution and is re-
corded in the history buffer when the instruction finishes execution. The exception
is not recognized until the faulting instruction reaches the head of the history
queue. When the exception is recognized, exception processing begins. The
queue is reversed, and the machine is restored to its state at the time the instruc-
tion was issued. Machine state is restored at a maximum rate of two floating-point
and two integer instructions per clock cycle.
To correctly restore the architectural state, the history buffer must record the value
of the destination before the instruction is executed. The destination of a store in-
struction, however, is in memory. It is not practical for the processor to always read
memory before writing it. Therefore, stores issue immediately to store buffers, but
do not update memory until all previous instructions have completed execution
without exception, i.e., until the store has reached the head of the history buffer.
The history buffer has enough storage to hold a total of six instructions. Of these,
a maximum of four can be integer instructions (including integer load or store in-
structions), and a maximum of three can be floating-point instructions (including
floating-point loads or stores). If the buffer includes an instruction with long latency,
it is possible (if a data dependency does not occur first) for issued instructions to
fill up the history buffer. If so, instruction issue halts until the long-latency operation
retires (along with any instructions following it that are ready to retire). Instructions
that can cause the history buffer to fill up include floating-point arithmetic instruc-
tions, integer divide instructions, and instructions that affect or use resources ex-
ternal to the processor (e.g., load/store instructions).
6.4 Implementation of Asynchronous Exceptions
When an enabled asynchronous exception is detected, the processor attempts to
retire as many instructions as possible. That is, all instructions that have completed
the writeback stage without generating exceptions are allowed to retire, provided
all instructions ahead of them in the history buffer have also completed the write-
back stage without generating exceptions.
ISSUED
HISTORY BUFFER QUEUE
QUEUE
HEAD
QUEUE
TAIL
RETIRED
INSTRUCTIONS
COMPLETED INSTRUCTIONS
WRITE BACK
INSTRUCTIONS
HIST BUF Q BLOCK
F
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