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RCPU
REFERENCE MANUAL
Notice in
Table 8-6
that during an instruction fetch (AT1 = 1) to internal memory or
to external memory resulting in a cache hit, a logic level of zero on the WR pin in-
dicates that the cycle is the result of an indirect change-of-flow. The indirect
change-of-flow attribute is also indicated by a cycle type encoding of 0001 when
AT1 = 1. Refer to
8.1.1.1 Marking the Indirect Change-of-Flow Attribute
for ad-
ditional information.
8.1.4 External Hardware During Program Trace
When program trace is needed, external hardware needs to record the status pins
(VF[0:2] and VFLS[0:1]) of each clock and record the address of all cycles marked
with the indirect change-of-flow attribute.
Program trace can be used in various ways. Two types of traces that can be imple-
mented are the back trace and the window trace.
8.1.4.1 Back Trace
A back trace provides a record of the program trace
before
some event occurred.
An example of such an event is some system failure.
When a back trace is needed, the external hardware should start sampling the sta-
tus pins and the address of all cycles marked with the indirect change-of-flow at-
tribute immediately after reset is negated. Since the ISCTL field in the ICTRL has
a value of is 0b00 (show all cycles) out of reset, all cycles marked with the indirect
change-of-flow attribute are visible on the external bus. VSYNC should be asserted
sometime after reset and negated when the programmed event occurs. VSYNC
must be asserted before the ISCTL encoding is changed to 0b11 (no show cycles),
if such an encoding is selected.
Note that in case the timing of the programmed event is unknown, it is possible to
use cyclic buffers.
After VSYNC is negated, the trace buffer will contain the program flow trace of the
program executed before the programmed event occurred.
8.1.4.2 Window Trace
Window trace provides a record of the program trace
between
two events. VSYNC
should be asserted between these two events.
After VSYNC is negated, the trace buffer will contain information describing the
program trace of the program executed between the two events.
8.1.4.3 Synchronizing the Trace Window to Internal CPU Events
In order to synchronize the assertion or negation of VSYNC to an event internal to
the processor, internal breakpoints can be used together with debug mode. This
method is available only when debug mode is enabled. (Refer to
8.4 Debug Mode
Functions
.)
The following steps enable the user to synchronize the trace window to events in-
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