
MOTOROLA
4-18
ADDRESSING MODES AND INSTRUCTION SET SUMMARY
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RCPU
REFERENCE MANUAL
such shifts simpler and easier to understand.
Any shift right algebraic instruction, followed by
addze
, can be used to divide quick-
ly by 2
n
.
Multiple-precision shifts can be programmed as shown in
APPENDIX B MULTI-
PLE-PRECISION SHIFTS
.
The integer shift instructions are summarized in
Table 4-6
.
Table 4-6 Integer Shift Instructions
Name
Mnemonic
Operand
Syntax
Operation
Shift Left
Word
slw
slw.
r
A
,r
S
,r
B
The contents of
r
S are shifted left the number of bits specified by
r
B[26:31]. Bits shifted out of position 0 are lost. Zeros are supplied to
the vacated positions on the right. The 32-bit result is placed into
r
A.
If
r
B[26] = 1, then
r
A is filled with zeros.
slw
slw.
Shift Left Word
Shift Left Word with CR Update. The dot suffix enables
the update of the condition register.
Shift Right
Word
srw
srw.
r
A
,r
S
,r
B
The contents of
r
S are shifted right the number of bits specified by
r
B[26:31]. Zeros are supplied to the vacated positions on the left. The
32-bit result is placed into
r
A.
If
r
B[26]=1, then
r
A is filled with zeros.
srw
srw.
Shift Right Word
Shift Right Word with CR Update. The dot suffix enables
the update of the condition register.
Shift Right
Algebraic
Word
Immediate
srawi
srawi.
r
A
,r
S
,
SH
The contents of
r
S are shifted right the number of bits specified by
operand SH. Bits shifted out of position 31 are lost. The 32-bit result is
sign extended and placed into
r
A. XER[CA] is set if
r
S contains a
negative number and any 1-bits are shifted out of position 31;
otherwise XER(CA) is cleared. An operand SH of zero causes
r
A to be
loaded with the contents of
r
S and XER[CA] to be cleared to zero.
srawi
srawi.
Shift Right Algebraic Word Immediate
Shift Right Algebraic Word Immediate with CR Update.
The dot suffix enables the update of the condition
register.
Shift Right
Algebraic
Word
sraw
sraw.
r
A
,r
S
,r
B
The contents of
r
S are shifted right the number of bits specified by
r
B[26:31]. The 32-bit result is placed into
r
A. XER[CA] is set to one if
r
S contains a negative number and any 1-bits are shifted out of
position 31; otherwise XER[CA] is cleared to zero. An operand (
r
B) of
zero causes
r
A to be loaded with the contents of
r
S, and XER[CA] to
be cleared to zero. If
r
B[26] = 1, then
r
A is filled with 32 sign bits (bit
0) from
r
S. If
r
B[26] = 0, then
r
A is filled from the left with sign bits.
Condition register field CR0 is set based on the value written into
r
A.
sraw
sraw.
Shift Right Algebraic Word
Shift Right Algebraic Word with CR Update. The dot suffix
enables the update of the condition register.
F
Freescale Semiconductor, Inc.
n
.