
MOTOROLA
6-6
EXCEPTIONS
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RCPU
REFERENCE MANUAL
Table 6-3 Exception Vectors and Conditions
Exception
Type
Vector Offset
Causing Conditions
Reserved
0x00000
Reserved
System reset
0x00100
A reset exception results when the RESET input to the processor is asserted.
Machine check
0x00200
A machine check exception results when the TEA signal is asserted internally or
externally.
—
0x00300
Reserved. (In the PowerPC architecture, this exception vector is reserved for
data access exceptions.)
—
0x00400
Reserved. (In the PowerPC architecture, this exception vector is reserved for
instruction access exceptions.)
External
interrupt
0x00500
An external interrupt occurs when the RCPU IRQ input signal is asserted.
Alignment
0x00600
An alignment exception is caused when the processor cannot perform a memory
access for one of the following reasons:
The operand of a floating-point load or store is not word-aligned.
The operand of a load- or store-multiple instruction is not word-aligned.
The operand of
lwarx
or
stwcx.
is not word-aligned.
In little-endian mode, an operand is not properly aligned.
In little-endian mode, the processor attempts to execute a multiple or string
instruction.
Program
0x00700
A program exception is caused by one of the following exception conditions:
Floating-point enabled exception — A floating-point enabled program
exception condition is generated when the following condition is met as a
result of a move to FPSCR instruction, move to MSR instruction, or return
from interrupt instruction:
(MSR[FE0] | MSR[FE1]) & FPSCR[FEX] = 1.
Privileged instruction — A privileged instruction type program exception is
generated when the execution of a privileged instruction is attempted and
the MSR register user privilege bit, MSR[PR], is set. This exception is also
generated for
mtspr
or
mfspr
with an invalid SPR field if SPR[0]=1 and
MSR[PR]=1.
Trap — A trap type program exception is generated when any of the
conditions specified in a trap instruction is met.
Floating-point
unavailable
0x00800
A floating-point unavailable exception is caused by an attempt to execute a
floating-point instruction (including floating-point load, store, and move
instructions) when the floating-point available bit is disabled, MSR[FP]=0.
Decrementer
0x00900
The decrementer exception occurs when the most significant bit of the
decrementer (DEC) register changes from zero to one.
Reserved
0x00A00
—
Reserved
0x00B00
—
System call
0x00C00
A system call exception occurs when a system call (
sc
) instruction is executed.
Trace
0x00D00
A trace exception occurs if MSR[SE] = 1 and any instruction other than
rfi
is
successfully completed, or if MSR[BE] = 1 and a branch is completed.
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