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MOTOROLA
8-13
The comparators are able to detect the following conditions: equal, not equal,
greater than, and less than. Greater than or equal and less than or equal are easily
obtained from these four conditions. (For more information refer to
8.2.1.3 Gener-
ating Six Compare Types
.) Using the AND-OR logic structures, in range and out
of range detection (on address and on data) are supported. Using the counters, it
is possible to program a breakpoint to be generated after an event is detected a
predefined number of times.
The L-data comparators can operate on integer data, floating-point single-preci-
sion data, and the integer value stored using the
stfiwx
instruction. Integer com-
parisons can be performed on bytes, half words, and words. The operands can be
treated as signed or unsigned values.
The comparators generate match events. The I-bus match events enter the I-bus
AND-OR logic, where the I-bus watchpoints and breakpoint are generated. When
asserted, the I-bus watchpoints may generate the I-bus breakpoint. Two of them
may decrement one of the counters. When a counter that is counting one of the
I-bus watchpoints expires, the I-bus breakpoint is asserted.
The I-bus watchpoints and the L-bus match events (address and data) enter the
L-bus AND-OR logic where the L-bus watchpoints and breakpoint are generated.
When asserted, the L-bus watchpoints may generate the L-bus breakpoint, or they
may decrement one of the counters. When a counter that is counting one of the
L-bus watchpoints expires, the L-bus breakpoint is asserted.
L-bus watchpoints can be qualified by I-bus watchpoints. If qualified, the L-bus
watchpoint occurs only if the L-bus cycle was the result of executing an instruction
that caused the qualifying I-bus watchpoint.
A watchpoint progresses in the machine along with the instruction that caused it
(fetch or load/store cycle). Watchpoints are reported on the external pins when the
associated instruction is retired.
8.2.1.1 Restrictions on Watchpoint Detection
There are cases when the same watchpoint can be detected more than once dur-
ing the execution of a single instruction. For example, the processor may detect an
L-bus watchpoint on more than one transfer when executing a load/store multiple
or string instruction or may detect an L-bus watchpoint on more than one byte when
working in byte mode. In these cases only one watchpoint of the same type is re-
ported for a single instruction. Similarly, only one watchpoint of the same type can
be counted in the counters for a single instruction.
Since watchpoint events are reported upon the retirement of the instruction that
caused the event, and more than one instruction can retire from the machine in one
clock, separate watchpoint events may be reported in the same clock. Moreover,
the same event, if detected on more than one instruction (e.g., tight loops, range
detection), in some cases is reported only once. However, the internal counters still
count correctly.
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Freescale Semiconductor, Inc.
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