
MOTOROLA
4-34
ADDRESSING MODES AND INSTRUCTION SET SUMMARY
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RCPU
REFERENCE MANUAL
Table 4-13 Integer Load Instructions
Name
Mnemonic
Operand
Syntax
Operation
Load Byte
and Zero
lbz
r
D
,d(r
A
)
The effective address is the sum (
r
A|0) + d. The byte in memory
addressed by the EA is loaded into register
r
D[24:31].
The remaining
bits in register
r
D are cleared to zero.
Load Byte
and Zero
Indexed
lbzx
r
D
,r
A
,r
B
The effective address is the sum (
r
A|0) + (
r
B). The byte in memory
addressed by the EA is loaded into register
r
D[24:31].
The remaining
bits in register
r
D are cleared to zero.
Load Byte
and Zero
with Update
lbzu
r
D
,d(r
A
)
The effective address (EA) is the sum (
r
A|0) + d. The byte in memory
addressed by the EA is loaded into register
r
D[24:31]. The remaining
bits in register
r
D are cleared to zero. The EA is placed into register
r
A.
The
PowerPC architecture defines load with update instructions with
r
A = 0 or
r
A =
r
D as invalid forms. In the RCPU, however, if
r
A = 0 then
the EA is written into R0. If
r
A =
r
D then
r
A is loaded from memory
location MEM(
r
A, N) where N is determined by the instruction operand
size.
Load Byte
and Zero
with Update
Indexed
lbzux
r
D
,r
A
,r
B
The effective address (EA) is the sum (
r
A|0) + (
r
B). The byte
addressed by the EA is loaded into register
r
D[24:31]. The remaining
bits in register
r
D are cleared to zero. The EA is placed into register
r
A.
The
PowerPC architecture defines load with update instructions with
r
A = 0 or
r
A =
r
D as invalid forms. In the RCPU, however, if
r
A = 0 then
the EA is written into R0. If
r
A =
r
D then
r
A is loaded from memory
location MEM(
r
A, N) where N is determined by the instruction operand
size.
Load
Half Word
and Zero
lhz
r
D
,d(r
A
)
The effective address is the sum (
r
A|0) + d. The half-word in memory
addressed by the EA is loaded into register
r
D[16:31]. The remaining
bits in
r
D are cleared to zero.
Load
Half Word
and Zero
Indexed
lhzx
r
D
,r
A
,r
B
The effective address is the sum (
r
A|0) + (
r
B). The half-word in
memory addressed by the EA is loaded into register
r
D[16:31]. The
remaining bits in register
r
D are cleared.
Load
Half Word
and Zero
with Update
lhzu
r
D
,d(r
A
)
The effective address is the sum (
r
A|0) + d. The half-word in memory
addressed by the EA is loaded into register
r
D[16:31]. The remaining
bits in register
r
D are cleared.
The EA is placed into register
r
A.
The
PowerPC architecture defines load with update instructions with
r
A = 0 or
r
A =
r
D as invalid forms. In the RCPU, however, if
r
A=0 then
the EA is written into R0. If
r
A =
r
D then
r
A is loaded from memory
location MEM(
r
A, N) where N is determined by the instruction operand
size.
F
Freescale Semiconductor, Inc.
n
.