參數(shù)資料
型號(hào)： TMX320VC5509AGHH
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： TMS320VC5509A Fixed-Point Digital Signal Processor
中文描述： TMS320VC5509A定點(diǎn)數(shù)字信號(hào)處理器
文件頁數(shù)： 96/144頁
文件大小： 1603K
代理商： TMX320VC5509AGHH
Electrical Specifications
96
November 2002 Revised January 2005
SPRS205D
5.7.2 Synchronous DRAM (SDRAM) Timings
Table 59 and Table 510 assume testing over recommended operating conditions (see Figure 58 through
Figure 514).
Table 59. Synchronous DRAM Cycle Timing Requirements
NO.
CV
DD
= 1.2 V
CV
DD
= 1.35 V
MIN
CV
DD
= 1.6 V
UNIT
MAX
MIN
MAX
M19
t
su(DV-CLKMEMH)
Setup time, read data valid before CLKMEM high
3
3
ns
M20
t
h(CLKMEMH-DV)
Hold time, read data valid after CLKMEM high
2
2
ns
M21
t
c(CLKMEM)
Cycle time, CLKMEM
9.26
7.52
ns
Maximum SDRAM operating frequency = 108 MHz. Actual attainable maximum operating frequency will depend on the quality of the PC board
design and the memory chip timing requirement.
Maximum SDRAM operating frequency = 133 MHz. Actual attainable maximum operating frequency will depend on the quality of the PC board
design and the memory chip timing requirement.
Table 510. Synchronous DRAM Cycle Switching Characteristics
NO.
PARAMETER
CV
DD
= 1.2 V
CV
DD
= 1.35 V
MIN
CV
DD
= 1.6 V
UNIT
MAX
MIN
MAX
M22
t
d(CLKMEMH-CEL)
t
d(CLKMEMH-CEH)
t
d(CLKMEMH-BEV)
t
d(CLKMEMH-BEIV)
t
d(CLKMEMH-AV)
t
d(CLKMEMH-AIV)
t
d(CLKMEMH-SDCASL)
t
d(CLKMEMH-SDCASH)
t
d(CLKMEMH-DV)
t
d(CLKMEMH-DIV)
t
d(CLKMEMH-SDWEL)
t
d(CLKMEMH-SDWEH)
t
d(CLKMEMH-SDA10V)
t
d(CLKMEMH-SDA10IV)
t
d(CLKMEMH-SDRASL)
t
d(CLKMEMH-SDRASH)
Delay time, CLKMEM high to CEx low
1.2
7
1.2
5
ns
M23
Delay time, CLKMEM high to CEx high
1.2
7
1.2
5
ns
M24
Delay time, CLKMEM high to BEx valid
1.2
7
1.2
5
ns
M25
Delay time, CLKMEM high to BEx invalid
1.2
7
1.2
5
ns
M26
Delay time, CLKMEM high to address valid
1.2
7
1.2
5
ns
M27
Delay time, CLKMEM high to address invalid
1.2
7
1.2
5
ns
M28
Delay time, CLKMEM high to SDCAS low
1.2
7
1.2
5
ns
M29
Delay time, CLKMEM high to SDCAS high
1.2
7
1.2
5
ns
M30
Delay time, CLKMEM high to data valid
1.2
7
1.2
5
ns
M31
Delay time, CLKMEM high to data invalid
1.2
7
1.2
5
ns
M32
Delay time, CLKMEM high to SDWE low
1.2
7
1.2
5
ns
M33
Delay time, CLKMEM high to SDWE high
1.2
7
1.2
5
ns
M34
Delay time, CLKMEM high to SDA10 valid
1.2
7
1.2
5
ns
M35
Delay time, CLKMEM high to SDA10 invalid
1.2
7
1.2
5
ns
M36
Delay time, CLKMEM high to SDRAS low
1.2
7
1.2
5
ns
M37
Delay time, CLKMEM high to SDRAS high
1.2
7
1.2
5
ns
M38
t
d(CLKMEMH–CKEL)
t
d(CLKMEMH–CKEH)
Delay time, CLKMEM high to CKE low
1.2
7
1.2
5
ns
M39
Delay time, CLKMEM high to CKE high
1.2
7
1.2
5
ns
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