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參數(shù)資料
| 型號(hào)： | TMX320VC5509AGHH |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | TMS320VC5509A Fixed-Point Digital Signal Processor |
| 中文描述： | TMS320VC5509A定點(diǎn)數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 14/144頁(yè) |
| 文件大?。?/td> | 1603K |
| 代理商： | TMX320VC5509AGHH |
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Introduction
14
November 2002 Revised January 2005
SPRS205D
2
Introduction
This section describes the main features of the TMS320VC5509A, lists the pin assignments, and describes
the function of each pin. This data manual also provides a detailed description section, electrical
specifications, parameter measurement information, and mechanical data about the available packaging.
NOTE:
This data manual is designed to be used in conjunction with the
TMS320C55x
DSP Functional
Overview
(literature number SPRU312), the
TMS320C55x DSP CPU Reference Guide
(literature
number SPRU371), and the
TMS320C55x DSP Peripherals Overview Reference Guide
(literature
number SPRU317).
Description
The TMS320VC5509A fixed-point digital signal processor (DSP) is based on the TMS320C55x DSP
generation CPU processor core. The C55x
DSP architecture achieves high performance and low power
through increased parallelism and total focus on reduction in power dissipation. The CPU supports an internal
bus structure that is composed of one program bus, three data read buses, two data write buses, and
additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to
three data reads and two data writes in a single cycle. In parallel, the DMA controller can perform up to two
data transfers per cycle independent of the CPU activity.
2.1
The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit multiplication
in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional 16-bit ALU. Use of
the ALUs is under instruction set control, providing the ability to optimize parallel activity and power
consumption. These resources are managed in the Address Unit (AU) and Data Unit (DU) of the C55x CPU.
The C55x DSP generation supports a variable byte width instruction set for improved code density. The
Instruction Unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions
for the Program Unit (PU). The Program Unit decodes the instructions, directs tasks to AU and DU resources,
and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution
of conditional instructions.
The general-purpose input and output functions and the10-bit A/D provide sufficient pins for status, interrupts,
and bit I/O for LCDs, keyboards, and media interfaces. The parallel interface operates in two modes, either
as a slave to a microcontroller using the HPI port or as a parallel media interface using the asynchronous EMIF.
Serial media is supported through two MultiMedia Card/Secure Digital (MMC/SD) peripherals and three
McBSPs.
The 5509A peripheral set includes an external memory interface (EMIF) that provides glueless access to
asynchronous memories like EPROM and SRAM, as well as to high-speed, high-density memories such as
synchronous DRAM. Additional peripherals include Universal Serial Bus (USB), real-time clock, watchdog
timer, I
2
C multi-master and slave interface, and a unique device ID. Three full-duplex multichannel buffered
serial ports (McBSPs) provide glueless interface to a variety of industry-standard serial devices, and
multichannel communication with up to 128 separately enabled channels. The enhanced host-port interface
(HPI) is a 16-bit parallel interface used to provide host processor access to 32K bytes of internal memory on
the 5509A. The HPI can be configured in either multiplexed or non-multiplexed mode to provide glueless
interface to a wide variety of host processors. The DMA controller provides data movement for six independent
channel contexts without CPU intervention, providing DMA throughput of up to two 16-bit words per cycle. Two
general-purpose timers, up to eight dedicated general-purpose I/O (GPIO) pins, and digital phase-locked loop
(DPLL) clock generation are also included.
The 5509A is supported by the industry’s award-winning eXpressDSP
, Code Composer Studio
Integrated
Development Environment (IDE), DSP/BIOS
, Texas Instruments’ algorithm standard, and the industry’s
largest third-party network. The Code Composer Studio IDE features code generation tools including a
C Compiler and Visual Linker, simulator, RTDX
, XDS510
emulation device drivers, and evaluation
modules. The 5509A is also supported by the C55x DSP Library which features more than 50 foundational
software kernels (FIR filters, IIR filters, FFTs, and various math functions) as well as chip and board support
libraries.
C55x, eXpressDSP, Code Composer Studio, DSP/BIOS, RTDX, and XDS510 are trademarks of Texas Instruments.
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| TMX320VC5509APGE | 制造商:Texas Instruments 功能描述: |
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| TMX320VC5509GHH31 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| TMX320VC5509PGE | 制造商:Rochester Electronics LLC 功能描述:AMADEUS - Bulk 制造商:Texas Instruments 功能描述: |
| TMX320VC5509PGE31 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
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