參數(shù)資料
型號： TMX320VC5509AGHH
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： TMS320VC5509A Fixed-Point Digital Signal Processor
中文描述： TMS320VC5509A定點(diǎn)數(shù)字信號處理器
文件頁數(shù)： 40/144頁
文件大?。?/td> 1603K
代理商： TMX320VC5509AGHH
Functional Overview
40
November 2002 Revised January 2005
SPRS205D
3.5.1 External Bus Selection Register (EBSR)
The External Bus Selection Register determines the mapping of the 14 (LQFP) or 21 (BGA) address signals,
16 data signals, and 15 control signals of the external parallel port. It also determines the mapping of the
McBSP or MMC/SD ports to Serial Port1 and Serial Port2. The External Bus Selection Register is
memory-mapped at port address 0x6C00. Once the bit fields of this register are changed, the routing of the
signals takes place on the next CPU clock cycle.
The reset value of the parallel port mode bit field is determined by the state of the GPIO0 pin at reset. If GPIO0
is high at reset, the full EMIF mode is enabled and the parallel port mode bit field is set to 01. If GPIO0 is low
at reset, the HPI multiplexed mode is enabled and the parallel port mode bit field is set to 11. After reset, the
parallel port should be selected to function in either EMIF mode or HPI mode. Dynamic switching of the parallel
port, once configured, is not recommended.
15
14
13
12
11
10
9
8
CLKOUT
Disable
OSC Disable
HIDL
BKE
SR STAT
HOLD
HOLDA
CKE SEL
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 1
R/W, 0
7
6
5
4
3
2
1
0
CKE EN
SR CMD
Serial Port2
Mode
Serial Port1
Mode
Parallel Port
Mode
R/W, 0
R/W, 0
R/W, 00
R/W, 00
R/W, 01 if GPIO0 = 1
11 if GPIO0 = 0
LEGEND:
R = Read, W = Write,
n
= value after reset
Figure 35. External Bus Selection Register
Table 35. External Bus Selection Register Bit Field Description
BITS
DESCRIPTION
15
CLKOUT disable.
CLKOUT disable = 0:
CLKOUT disable = 1:
CLKOUT enabled
CLKOUT disabled
14
Oscillator disable.
Works with IDLE instruction to put the clock generation domain into IDLE mode.
OSC disable = 0:
OSC disable = 1:
Oscillator enabled
Oscillator disabled
13
Host mode idle bit.
(Applicable
only
if the parallel bus is configured as EHPI.)
When the parallel bus is set to EHPI mode, the clock domain is not allowed to go to idle, so a host processor can
access the DSP internal memory. The HIDL bit works around this restriction and allows the DSP to idle the clock
domain and the EHPI. When the clock domain is in idle, a host processor will not be able to access the DSP
memory.
HIDL = 0:
HIDL = 1:
Host access to DSP enabled. Idling EHPI and clock domain is not allowed.
Idles the HPI and the clock domain upon execution of the IDLE instruction when the parallel
port mode is set to 10 or 11 selecting HPI mode. In addition, bit 4 of the Idle Control Register
must be set to 1 prior to the execution of the IDLE instruction.
Bus keeper enable.
12
BKE = 0:
BKE = 1:
Bus keeper, pullups/pulldowns enabled
Bus keeper, pullups/pulldowns disabled
Function available when the port or pins configured as input.
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