參數(shù)資料
型號： TMX320VC5509AGHH
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： TMS320VC5509A Fixed-Point Digital Signal Processor
中文描述： TMS320VC5509A定點數(shù)字信號處理器
文件頁數(shù)： 19/144頁
文件大?。?/td> 1603K
代理商： TMX320VC5509AGHH
Introduction
19
November 2002 Revised January 2005
SPRS205D
2.3
Signal Descriptions
Table 23 lists each signal, function, and operating mode(s) grouped by function. See Section 2.2 for pin
locations based on package type.
Table 23. Signal Descriptions
TERMINAL
NAME
MULTIPLEXED
SIGNAL NAME
I/O/Z
FUNCTION
BK
RESET
CONDITION
PARALLEL BUS
A[13:0]
I/O/Z
A subset of the parallel address bus A13A0 of the C55x
DSP core
bonded to external pins. These pins serve in one of three functions: HPI
address bus (HPI.HA[13:0]), EMIF address bus (EMIF.A[13:0]), or
general-purpose I/O (GPIO.A[13:0]). The initial state of these pins
depends on the GPIO0 pin. See Section 3.5.1 for more information.
The address bus has a bus holder feature that eliminates passive
component requirement and the power dissipation associated with them.
The bus holders keep the address bus at the previous logic level when the
bus goes into a high-impedance state.
HPI address bus. HPI.HA[13:0] is selected when the Parallel Port Mode bit
field of the External Bus Selection Register is 10. This setting enables the
HPI in non-multiplexed mode.
GPIO0 = 1:
HPI.HA[13:0]
I
HPI.HA[13:0] provides DSP internal memory access to host. In
non-multiplexed mode, these signals are driven by an external host as
address lines.
EMIF address bus. EMIF.A[13:0] is selected when the Parallel Port Mode
bit field of the External Bus Selection Register is 01. This setting enables
the full EMIF mode and the EMIF drives the parallel port address bus. The
internal A[14] address is exclusive-ORed with internal A[0] address and
the result is routed to the A[0] pin.
BK
Output,
EMIF.A[13:0]
GPIO0 = 0:
EMIF.A[13:0]
O/Z
Input,
HPI.HA[13:0]
GPIO.A[13:0]
I/O/Z
General-purpose I/O address bus. GPIO.A[13:0] is selected when the
Parallel Port Mode bit field of the External Bus Selection Register is 11.
This setting enables the HPI in multiplexed mode with the Parallel Port
GPIO register controlling the parallel port address bus. GPIO is also
selected when the Parallel Port Mode bit field is 00, enabling the Data
EMIF mode.
EMIF address bus A
′
[0]. This pin is not multiplexed with EMIF.A[14] and is
used as the least significant external address pin on the BGA package.
A
′
[0]
(BGA only)
I = Input, O = Output, S = Supply, Hi-Z = High-impedance
BK = bus keeper (the bus keeper maintains the previous voltage level during reset or while the output pin is not driven), PU = pullup,
PD = pulldown, H = hysteresis input buffer, FS = fail-safe buffer
EMIF.A
′
[0]
O/Z
Output
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TMX320VC5509APGE 制造商:Texas Instruments 功能描述:
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