參數(shù)資料
型號(hào)： TMX320VC5509AGHH
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： TMS320VC5509A Fixed-Point Digital Signal Processor
中文描述： TMS320VC5509A定點(diǎn)數(shù)字信號(hào)處理器
文件頁(yè)數(shù)： 85/144頁(yè)
文件大?。?/td> 1603K
代理商： TMX320VC5509AGHH
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Electrical Specifications
85
November 2002 Revised January 2005
SPRS205D
5.3.2 Electrical Characteristics Over Recommended Operating Case Temperature
Range for CV
DD
= 1.35 V (144 MHz) (Unless Otherwise Noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DN and DP
USBV
DD
= 3.0 V3.6 V,
I
OH
= 300
μ
A
2.8
USBV
DD
V
OH
High-level output voltage
PU
USBV
DD
= 3.0 V3.6 V,
I
OH
= 300
μ
A
0.9 * USBV
DD
USBV
DD
V
All other outputs
DV
DD
= 2.7 V3.6 V,
I
OH
= MAX
0.75 * DV
DD
SDA & SCL
DN and DP
At 3 mA sink current
0
0.4
V
OL
Low-level output voltage
I
OL
= 3.0 mA
I
OL
= MAX
0.3
V
All other outputs
0.4
I
IZ
high-impedance
Output-only or
I/O pins with bus
keepers (enabled)
DV
DD
= MAX,
V
O
= V
SS
to DV
DD
300
300
μ
A
Input current for outputs in
All other output-only
or I/O pins
DV
DD
= MAX
V
O
= V
SS
to DV
DD
5
5
Input pins with
internal pulldown
(enabled)
DV
DD
= MAX,
V
I
= V
SS
to DV
DD
30
300
I
I
Input current
Input pins with
internal pullup
(enabled)
DV
DD
= MAX,
V
I
= V
SS
to DV
DD
300
30
μ
A
X2/CLKIN
DV
DD
= MAX,
V
I
= V
SS
to DV
DD
50
50
All other input-only
pins
DV
DD
= MAX,
V
I
= V
SS
to DV
DD
5
5
I
DDC
CV
DD
Supply current, CPU + internal memory access
§
CV
DD
= 1.35 V
CPU clock = 144 MHz
T
C
= 25 C
0.51
mA/
MHz
I
DDP
DV
DD
supply current, pins active
DV
DD
= 3.3 V
CPU clock = 144 MHz
T
C
= 25 C
5.5
mA
I
DDC
CV
DD
supply current, standby
#
Oscillator disabled.
All domains in
low-power state
CV
DD
= 1.35 V
T
C
= 25 C
125
μ
A
I
DDP
DV
DD
supply current, standby
Oscillator disabled.
All domains in
low-power state.
DV
DD
= 3.3 V
No I/O activity
T
C
= 25 C
10
μ
A
C
i
Input capacitance
3
pF
C
o
Output capacitance
3
pF
USB I/O pins DP and DN can tolerate a short circuit at D+ and D to 0 V or 5 V, as long as the recommended series resistors (see Figure 542)
are connected between the D+ and DP (package), and the D and DN (package). Do not apply a short circuit to the USB I/O pins DP and
DN in absence of the series resistors.
The I
2
C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down.
§
CPU executing 75% Dual MAC + 25% ADD with moderate data bus activity (table of sine values). CPU and CLKGEN (DPLL) domain are active.
All other domains are idled. See the
TMS320VC5509A Power Consumption Summary
Application Report (literature number SPRAA04).
One word of a table of a 16-bit sine value is written to the EMIF every 250 ns (64 Mbps). Each EMIF output pin is connected to a 10-pF load.
#
In CLKGEN domain idle mode, X2/CLKIN becomes output and is driven low to stop external crystals (if used) from oscillating. Standby current
will be higher if an external clock source tries to drive the X2/CLKIN pin during this time.
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