參數(shù)資料
型號(hào)： TMX320VC5509AGHH
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： TMS320VC5509A Fixed-Point Digital Signal Processor
中文描述： TMS320VC5509A定點(diǎn)數(shù)字信號(hào)處理器
文件頁數(shù)： 91/144頁
文件大?。?/td> 1603K
代理商： TMX320VC5509AGHH
Electrical Specifications
91
November 2002 Revised January 2005
SPRS205D
5.6.4 Clock Generation in Lock Mode (DPLL Synthesis Enabled)
The frequency of the reference clock provided at the X2/CLKIN pin can be multiplied by a synthesis factor of
N to generate the internal CPU clock cycle. The synthesis factor is determined by:
N
=
M
D
L
where: M = the multiply factor set in the PLL_MULT field of the clock mode register
D
L
= the divide factor set in the PLL_DIV field of the clock mode register
Valid values for M are (multiply by) 2 to 31. Valid values for D
L
are (divide by) 1, 2, 3, and 4.
For detailed information on clock generation configuration, see the
TMS320C55x DSP Peripherals Overview
Reference Guide
(literature number SPRU317).
Table 54 and Table 55 assume testing over recommended operating conditions and H = 0.5t
c(CO)
(see
Figure 54).
Table 54. Multiply-By-N Clock Option Timing Requirements
NO.
CV
DD
= 1.2 V
CV
DD
= 1.35 V
CV
DD
= 1.6 V
MIN
20
UNIT
MAX
C1
t
c(CI)
t
f(CI)
t
r(CI)
t
w(CIL)
t
w(CIH)
Cycle time, X2/CLKIN
DPLL synthesis enabled
400
ns
C2
Fall time, X2/CLKIN
4
ns
C3
Rise time, X2/CLKIN
4
ns
C10
Pulse duration, CLKIN low
6
ns
C11
Pulse duration, CLKIN high
6
ns
The clock frequency synthesis factor and minimum X2/CLKIN cycle time should be chosen such that the resulting CLKOUT cycle time is within
the specified range (t
c(CO)
). If an external crystal is used, the X2/CLKIN cycle time is limited by the crystal frequency range listed in Table 51.
Table 55. Multiply-By-N Clock Option Switching Characteristics
NO.
PARAMETER
CV
DD
= 1.2 V
MIN
TYP
t
c(CI)*
N
CV
DD
= 1.35 V
MIN
TYP
t
c(CI)*
N
CV
DD
= 1.6 V
MIN
TYP
t
c(CI)*
N
UNIT
MAX
MAX
MAX
C4
t
c(CO)
t
f(CO)
t
r(CO)
Cycle time, CLKOUT
9.26
1600
6.95
1600
5
1600
ns
C6
Fall time, CLKOUT
1
1
1
ns
C7
Rise time, CLKOUT
1
1
1
ns
C8
t
w(COL)
Pulse duration, CLKOUT
low
H 1
H + 1
H 1
H + 1
H 1
H + 1
ns
C9
t
w(COH)
Pulse duration, CLKOUT
high
H 1
H + 1
H 1
H + 1
H 1
H + 1
ns
C12
t
d(CI–CO)
Delay time, X2/CLKIN
high/low to CLKOUT high/
low
5
15
25
5
15
25
5
15
25
ns
N = Clock frequency synthesis factor
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