參數(shù)資料
型號: TMX320VC5509AGHH
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號處理
英文描述: TMS320VC5509A Fixed-Point Digital Signal Processor
中文描述: TMS320VC5509A定點(diǎn)數(shù)字信號處理器
文件頁數(shù): 3/144頁
文件大?。?/td> 1603K
代理商: TMX320VC5509AGHH
Revision History
3
November 2002 Revised January 2005
SPRS205D
REVISION HISTORY
This data sheet revision history highlights the technical changes made to the SPRS205C device-specific data
sheet to make it an SPRS205D revision.
Scope:
Added Section 4.1, Notices Concerning JTAG (IEEE 1149.1) Boundary Scan Test Capability; added
179-terminal ZHH lead-free package; removed Secure ROM (SROM); added Package Addendum, etc.
PAGE(S)
NO.
ADDITIONS/CHANGES/DELETIONS
Global:
added 179-terminal ZHH lead-free package
deleted Section 3.1.4, Secure ROM
deleted Table 340, Secure ROM Register
moved “Package Thermal Resistance Characteristics” section to Section 6, Mechanical Data
added Package Addendum
13
Section 1, TMS320VC5509A Features:
added “179-Terminal Lead-Free MicroStar BGA
(Ball Grid Array) (ZHH Suffix)” feature
19
Table 23, Signal Descriptions:
HPI.HRDY: changed value of “I/O/Z” column from “O/Z” to “O”
33
Section 3.1.3, On-Chip Read-Only Memory (ROM):
deleted “The 16K ROM blocks at FFC000 to FFFFFF can be configured as secure ROM. (See Section 3.1.4.)” from
“The one-wait-state ROM is located at the byte address range FF0000hFFFFFFh ...” paragraph
34
Figure 32, TMS320VC5509A Memory Map (PGE Package):
removed SROM block
35
Section 3.1.4.2, GHH and ZHH Package Memory Map:
updated section to include 179-terminal ZHH package
35
Figure 33, TMS320VC5509A Memory Map (GHH and ZHH Packages):
removed SROM block
40
Section 3.5.1, External Bus Selection Register (EBSR):
appended “After reset, the parallel port should be selected to function in either EMIF mode or HPI mode. Dynamic
switching of the parallel port, once configured, is not recommended.” to “The reset value of the parallel port mode bit field
is determined by ...” paragraph
47
Section 3.6.2, Address Bus General-Purpose I/O:
appended “Note that the AGPIOEN bits should be set prior to setting the AGPIODIR bits.” to “The 16 address signals,
EMIF.A[150], can also be individually enabled as GPIO ...” paragraph
67
Table 333, I
2
C Module Registers:
0x3C0B: changed “I
2
C General-Purpose Register” (I2CGPIO) to “Reserved”
77
Section 4:
renamed section from “Documentation Support” to “Support”
77
Section 4, Support:
added Section 4.1, Notices Concerning JTAG (IEEE 1149.1) Boundary Scan Test Capability
added Section 4.1.1, Initialization Requirements for Boundary Scan Test
added Section 4.1.2, Boundary Scan Description Language (BSDL) Model
77
Added section title “4.2 Documentation Support”
78
Updated Section 4.3, Device and Development-Support Tool Nomenclature
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