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參數(shù)資料
| 型號(hào)： | TMX320VC5509AGHH |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | TMS320VC5509A Fixed-Point Digital Signal Processor |
| 中文描述： | TMS320VC5509A定點(diǎn)數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 47/144頁(yè) |
| 文件大?。?/td> | 1603K |
| 代理商： | TMX320VC5509AGHH |
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Functional Overview
47
November 2002 Revised January 2005
SPRS205D
15
8
7
6
5
4
3
2
1
0
Reserved
IO7D
IO6D
IO5D
(BGA)
IO4D
IO3D
IO2D
IO1D
IO0D
R00000000
R/Wpin
R/Wpin
R/Wpin
R/Wpin
R/Wpin
R/Wpin
R/Wpin
R/Wpin
LEGEND:
R = Read, W = Write,
pin
= value present on the pin (IO7IO0 default to inputs after reset)
Figure 39. I/O Data Register (IODATA) Bit Layout
Table 310. I/O Data Register (IODATA) Bit Functions
BIT
NO.
BIT
NAME
RESET
VALUE
FUNCTION
158
Reserved
0
These bits are reserved and are unaffected by writes.
70
IOxD
pin
IOx Data Bit.
If IOx is configured as an input (IOxDIR = 0 in IODIR):
IOxD = 0
The signal on the IOx pin is low.
IOxD = 1
The signal on the IOx pin is high.
If IOx is configured as an output (IOxDIR = 1 in IODIR):
IOxD = 0
Drive the signal on the IOx pin low.
IOxD = 1
Drive the signal on the IOx pin high.
The GPIO5 pin is available on the BGA package only.
pin
= value present on the pin (IO7IO0 default to inputs after reset)
3.6.2 Address Bus General-Purpose I/O
The 16 address signals, EMIF.A[150], can also be individually enabled as GPIO when the Parallel Port Mode
bit field of the External Bus Selection Register is set for Data EMIF (00) or Multiplexed EHPI mode (11). These
pins are controlled by three registers: the enable register, AGPIOEN, determines if the pins serve as GPIO
or address (Figure 310); the direction register, AGPIODIR, determines if the GPIO enabled pin is an input
or output (Figure 311); and the data register, AGPIODATA, determines the logic states of the pins in
general-purpose I/O mode (Figure 312). Note that the AGPIOEN bits should be set prior to setting the
AGPIODIR bits.
15
14
13
12
11
10
9
8
AIOEN15
(BGA)
AIOEN14
(BGA)
AIOEN13
AIOEN12
AIOEN11
AIOEN10
AIOEN9
AIOEN8
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
7
6
5
4
3
2
1
0
AIOEN7
AIOEN6
AIOEN5
AIOEN4
AIOEN3
AIOEN2
AIOEN1
AIOEN0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
LEGEND:
R = Read, W = Write,
n
= value after reset
Figure 310. Address/GPIO Enable Register (AGPIOEN) Bit Layout
Table 311. Address/GPIO Enable Register (AGPIOEN) Bit Functions
BIT
NO.
BIT
NAME
RESET
VALUE
FUNCTION
150
AIOENx
0
Enable or disable GPIO function of Address Bus of EMIF. AIOEN15 and AIOEN14 are only available in
BGA package.
AIOENx = 0
GPIO function of Ax line is disabled; i.e., Ax has address function.
AIOENx = 1
GPIO function of Ax line is enabled; i.e., Ax has GPIO function.
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| TMX320VC5509APGE | 制造商:Texas Instruments 功能描述: |
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| TMX320VC5509GHH31 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| TMX320VC5509PGE | 制造商:Rochester Electronics LLC 功能描述:AMADEUS - Bulk 制造商:Texas Instruments 功能描述: |
| TMX320VC5509PGE31 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
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