參數(shù)資料
型號： TMX320VC5509AGHH
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： TMS320VC5509A Fixed-Point Digital Signal Processor
中文描述： TMS320VC5509A定點數(shù)字信號處理器
文件頁數(shù)： 65/144頁
文件大?。?/td> 1603K
代理商： TMX320VC5509AGHH
Functional Overview
65
November 2002 Revised January 2005
SPRS205D
Table 329. Multichannel Serial Port #1
PORT ADDRESS
(WORD)
REGISTER NAME
DESCRIPTION
RESET VALUE
0x2C00
DRR2_1[15:0]
Data Receive Register 2, McBSP #1
0000 0000 0000 0000
0x2C01
DRR1_1[15:0]
Data Receive Register 1, McBSP #1
0000 0000 0000 0000
0x2C02
DXR2_1[15:0]
Data Transmit Register 2, McBSP #1
0000 0000 0000 0000
0x2C03
DXR1_1[15:0]
Data Transmit Register 1, McBSP #1
0000 0000 0000 0000
0x2C04
SPCR2_1[15:0]
Serial Port Control Register 2, McBSP #1
0000 0000 0000 0000
0x2C05
SPCR1_1[15:0]
Serial Port Control Register 1, McBSP #1
0000 0000 0000 0000
0x2C06
RCR2_1[15:0]
Receive Control Register 2, McBSP #1
0000 0000 0000 0000
0x2C07
RCR1_1[15:0]
Receive Control Register 1, McBSP #1
0000 0000 0000 0000
0x2C08
XCR2_1[15:0]
Transmit Control Register 2, McBSP #1
0000 0000 0000 0000
0x2C09
XCR1_1[15:0]
Transmit Control Register 1, McBSP #1
0000 0000 0000 0000
0x2C0A
SRGR2_1[15:0]
Sample Rate Generator Register 2, McBSP #1
0020 0000 0000 0000
0x2C0B
SRGR1_1[15:0]
Sample Rate Generator Register 1, McBSP #1
0000 0000 0000 0001
0x2C0C
MCR2_1[15:0]
Multichannel Control Register 2, McBSP #1
0000 0000 0000 0000
0x2C0D
MCR1_1[15:0]
Multichannel Control Register 1, McBSP #1
0000 0000 0000 0000
0x2C0E
RCERA_1[15:0]
Receive Channel Enable Register Partition A, McBSP #1
0000 0000 0000 0000
0x2C0F
RCERB_1[15:0]
Receive Channel Enable Register Partition B, McBSP #1
0000 0000 0000 0000
0x2C10
XCERA_1[15:0]
Transmit Channel Enable Register Partition A, McBSP #1
0000 0000 0000 0000
0x2C11
XCERB_1[15:0]
Transmit Channel Enable Register Partition B, McBSP #1
0000 0000 0000 0000
0x2C12
PCR1[15:0]
Pin Control Register, McBSP #1
0000 0000 0000 0000
0x2C13
RCERC_1[15:0]
Receive Channel Enable Register Partition C, McBSP #1
0000 0000 0000 0000
0x2C14
RCERD_1[15:0]
Receive Channel Enable Register Partition D, McBSP #1
0000 0000 0000 0000
0x2C15
XCERC_1[15:0]
Transmit Channel Enable Register Partition C, McBSP #1
0000 0000 0000 0000
0x2C16
XCERD_1[15:0]
Transmit Channel Enable Register Partition D, McBSP #1
0000 0000 0000 0000
0x2C17
RCERE_1[15:0]
Receive Channel Enable Register Partition E, McBSP #1
0000 0000 0000 0000
0x2C18
RCERF_1[15:0]
Receive Channel Enable Register Partition F, McBSP #1
0000 0000 0000 0000
0x2C19
XCERE_1[15:0]
Transmit Channel Enable Register Partition E, McBSP #1
0000 0000 0000 0000
0x2C1A
XCERF_1[15:0]
Transmit Channel Enable Register Partition F, McBSP #1
0000 0000 0000 0000
0x2C1B
RCERG_1[15:0]
Receive Channel Enable Register Partition G, McBSP #1
0000 0000 0000 0000
0x2C1C
RCERH_1[15:0]
Receive Channel Enable Register Partition H, McBSP #1
0000 0000 0000 0000
0x2C1D
XCERG_1[15:0]
Transmit Channel Enable Register Partition G, McBSP #1
0000 0000 0000 0000
0x2C1E
Hardware reset; x denotes a “don’t care.”
XCERH_1[15:0]
Transmit Channel Enable Register Partition H, McBSP #1
0000 0000 0000 0000
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