參數(shù)資料
型號： TMX320VC5509AGHH
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： TMS320VC5509A Fixed-Point Digital Signal Processor
中文描述： TMS320VC5509A定點(diǎn)數(shù)字信號處理器
文件頁數(shù)： 74/144頁
文件大小： 1603K
代理商： TMX320VC5509AGHH
Functional Overview
74
November 2002 Revised January 2005
SPRS205D
3.11.1
IFR and IER Registers
The IFR0 (Interrupt Flag Register 0) and IER0 (Interrupt Enable Register 0) bit layouts are shown in
Figure 320.
NOTE:
Some of the interrupts are shared between multiple interrupt sources. All sources for
a particular bit are internally combined using a logic OR function so that no additional user
configuration is required to select the interrupt source. In the case of the serial port, the shared
functions are mutually exclusive so that only one of the interrupt sources will be active at a time
in a given system. For example: It is not possible to use McBSP2 and MMC/SD2
simultaneously. However, in the case of INT3/WDTINT it is possible to have active interrupts
simultaneously from both the external INT3 source and the watchdog timer. When an interrupt
is detected in this bit, the watchdog timer status register should be polled to determine if the
watchdog timer is the interrupt source.
15
14
13
12
11
10
9
8
DMAC5
DMAC4
XINT2/
MMCSD2
RINT2
INT3/
WDTINT
DSPINT
DMAC1
USB
R/W0
R/W0
R/W0
R/W0
R/W0
R/W0
R/W0
R/W0
7
6
5
4
3
2
1
0
XINT1/
MMCSD1
RINT1
RINT0
TINT0
INT2
INT0
Reserved
R/W0
R/W0
R/W0
R/W0
R/W0
R/W0
R/W00
LEGEND:
R = Read, W = Write,
n
= value after reset
Figure 320. IFR0 and IER0 Bit Locations
Table 341. IFR0 and IER0 Register Bit Fields
BIT
FUNCTION
NUMBER
NAME
15
DMAC5
DMA channel 5 interrupt flag/mask bit
14
DMAC4
DMA channel 4 interrupt flag/mask bit
13
XINT2/MMCSD2
This bit is used as either the McBSP2 transmit interrupt flag/mask bit, the MMC/SD2 interrupt
flag/mask bit.
12
RINT2
McBSP2 receive interrupt flag/mask bit.
11
INT3/WDTINT
This bit is used as either the external user interrupt 3 flag/mask bit, or the watchdog timer interrupt
flag/mask bit.
10
DSPINT
HPI host-to-DSP interrupt flag/mask.
9
DMAC1
DMA channel 1 interrupt flag/mask bit
8
USB
USB interrupt flag/mask bit.
7
XINT1/MMCSD1
This bit is used as either the McBSP1 transmit interrupt flag/mask bit, the MMC/SD1 interrupt
flag/mask bit.
6
RINT1
McBSP1 receive interrupt flag/mask bit.
5
RINT0
McBSP0 receive interrupt flag bit
4
TINT0
Timer 0 interrupt flag bit
3
INT2
External interrupt 2 flag bit
2
INT0
External interrupt 0 flag bit
10
Reserved for future expansion. These bits should always be written with 0.
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