參數(shù)資料
型號(hào)： TMX320VC5509AGHH
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： TMS320VC5509A Fixed-Point Digital Signal Processor
中文描述： TMS320VC5509A定點(diǎn)數(shù)字信號(hào)處理器
文件頁數(shù)： 23/144頁
文件大?。?/td> 1603K
代理商： TMX320VC5509AGHH
Introduction
23
November 2002 Revised January 2005
SPRS205D
Table 23. Signal Descriptions (Continued)
TERMINAL
NAME
RESET
CONDITION
BK
FUNCTION
I/O/Z
MULTIPLEXED
SIGNAL NAME
PARALLEL BUS (CONTINUED)
EMIF byte enable 0 control or HPI byte identification. This pin serves in one
of two functions: EMIF byte enable 0 control (EMIF.BE0) or HPI byte
identification (HPI.HBE0). The initial state of this pin depends on the
GPIO0 pin. See Section 3.5.1 for more information.
C8
I/O/Z
GPIO0 = 1:
Output,
EMIF.BE0
EMIF.BE0
O/Z
Active-low EMIF byte enable 0 control. EMIF.BE0 is selected when the
Parallel Port Mode bit field of the External Bus Selection Register is set to
00 or 01.
BK
GPIO0 = 0:
Input,
HPI.HBE0
HPI.HBE0
I
HPI byte identification. This pin, in conjunction with HPI.HBE1, identifies
the first or second byte of the transfer. HPI.HBE0 is selected when the
Parallel Port Mode bit field is set to 10 or 11.
C9
I/O/Z
EMIF byte enable 1 control or HPI byte identification. This pin serves in one
of two functions: EMIF byte enable 1 control (EMIF.BE1) or HPI byte
identification (HPI.HBE1). The initial state of this pin depends on the
GPIO0 pin. See Section 3.5.1 for more information.
GPIO0 = 1:
Output,
EMIF.BE1
EMIF.BE1
O/Z
Active-low EMIF byte enable 1 control. EMIF.BE1 is selected when the
Parallel Port Mode bit field of the External Bus Selection Register is set to
00 or 01.
BK
GPIO0 = 0:
Input,
HPI.HBE1
HPI.HBE1
I
HPI byte identification. This pin, in conjunction with HPI.HBE0, identifies
the first or second byte of the transfer. HPI.HBE1 is selected when the
Parallel Port Mode bit field is set to 10 or 11.
C10
I/O/Z
EMIF SDRAM row strobe, HPI address strobe, or general-purpose IO12.
This pin serves in one of three functions: EMIF SDRAM row strobe
(EMIF.SDRAS), HPI address strobe (HPI.HAS), or general-purpose IO12
(GPIO12). The initial state of this pin depends on the GPIO0 pin. See
Section 3.5.1 for more information.
GPIO0 = 1:
Output,
EMIF.SDRAS
EMIF.SDRAS
O/Z
Active-low EMIF SDRAM row strobe. EMIF.SDRAS is selected when the
Parallel Port Mode bit field of the External Bus Selection Register is set to
00 or 01.
BK
GPIO0 = 0:
Input,
HPI.HAS
HPI.HAS
I
Active-low HPI address strobe. This signal latches the address in the HPIA
register in the HPI Multiplexed mode. HPI.HAS is selected when the
Parallel Port Mode bit field is set to 11.
GPIO12
I/O/Z
General-purpose IO12. GPIO12 is selected when the Parallel Port Mode
bit field is set to 10.
I = Input, O = Output, S = Supply, Hi-Z = High-impedance
BK = bus keeper (the bus keeper maintains the previous voltage level during reset or while the output pin is not driven), PU = pullup,
PD = pulldown, H = hysteresis input buffer, FS = fail-safe buffer
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