參數(shù)資料
型號： TMX320VC5509AGHH
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： TMS320VC5509A Fixed-Point Digital Signal Processor
中文描述： TMS320VC5509A定點(diǎn)數(shù)字信號處理器
文件頁數(shù)： 106/144頁
文件大?。?/td> 1603K
代理商： TMX320VC5509AGHH
Electrical Specifications
106
November 2002 Revised January 2005
SPRS205D
5.8.3 Warm Reset
Table 514 and Table 515 assume testing over recommended operating conditions (see Figure 517).
Table 514. Reset Timing Requirements
NO.
CV
DD
= 1.2 V
CV
DD
= 1.35 V
MIN
3P
CV
DD
= 1.6 V
UNIT
MAX
MIN
3P
MAX
R4
t
w(RSL)
Pulse width, reset low
ns
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
Table 515. Reset Switching Characteristics
NO.
PARAMETER
CV
DD
= 1.2 V
CV
DD
= 1.35 V
MIN
CV
DD
= 1.6 V
UNIT
MAX
MIN
MAX
R5
t
d(RSTH-BKV)
t
d(RSTH-HIGHV)
t
d(RSTL-ZIV)
t
d(RSTH-ZV)
Delay time, reset high to BK group valid
Delay time, reset high to High group valid
§
Delay time, reset low to Z group invalid
Delay time, reset high to Z group valid
38P + 15
38P + 15
ns
R6
38P + 15
38P + 15
ns
R7
1P + 15
1P + 15
ns
R8
38P + 15
38P + 15
ns
P = 1/CPU clock frequency in ns. For example, when CPU is running at 200 MHz, P = 5 ns.
BK group: Pins with bus keepers, holds previous state during reset. Following low-to-high transition of RESET, these pins go to their post-reset
logic state.
BK group pins: A’[0], A[15:0], D[15:0], C[14:2], C0, GPIO5, S13, and S23
§
High group: Following low-to-high transition of RESET, these pins go to logic-high state.
High group pins: C1[HPI.HINT], XF
Z group: Bidirectional pins which become input or output pins. Following low-to-high transition of RESET, these pins go to high-impedance state.
Z group pins: C1[EMIF.AOE], GPIO[7:6, 4:0], TIN/TOUT0, SDA, SCL, CLKR0, FSRX0, CLKX0, DX0, FSX0, S[25:24, 22:20, 15:14, 12:10],
A[20:16]
RESET
BK Group
High Group
Z Group
§
R5
R7
R6
R8
BK group pins: A’[0], A[15:0], D[15:0], C[14:2], C0, GPIO5, S13, and S23
High group pins: C1[HPI.HINT], XF
§
Z group pins: C1[EMIF.AOE], GPIO[7:6, 4:0], TIN/TOUT0, SDA, SCL, CLKR0, FSRX0, CLKX0, DX0, FSX0, S[25:24, 22:20, 15:14, 12:10],
A[20:16]
Figure 517. Reset Timings
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