參數(shù)資料
型號(hào)： TMX320VC5509AGHH
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： TMS320VC5509A Fixed-Point Digital Signal Processor
中文描述： TMS320VC5509A定點(diǎn)數(shù)字信號(hào)處理器
文件頁數(shù)： 26/144頁
文件大?。?/td> 1603K
代理商： TMX320VC5509AGHH
Introduction
26
November 2002 Revised January 2005
SPRS205D
Table 23. Signal Descriptions (Continued)
TERMINAL
NAME
RESET
CONDITION
BK
FUNCTION
I/O/Z
MULTIPLEXED
SIGNAL NAME
TIMER SIGNALS
TIN/TOUT0
I/O/Z
Timer0 Input/Output. When output, TIN/TOUT0 signals a pulse or a
change of state when the on-chip timer counts down past zero. When
input, TIN/TOUT0 provides the clock source for the internal timer module.
At reset, this pin is configured as an input.
NOTE: Only the Timer0 signal is brought out. The Timer1 signal is
terminated internally and is not available for external use.
H
Input
REAL-TIME CLOCK
RTCINX1
I
Real-Time Clock Oscillator input
Input
RTCINX2
O
Real-Time Clock Oscillator output
Output
I
2
C
SDA
I/O/Z
I
2
C (bidirectional) data. At reset, this pin is in high-impedance mode.
I
2
C (bidirectional) clock. At reset, this pin is in high-impedance mode.
H
Hi-Z
SCL
I/O/Z
H
Hi-Z
MULTICHANNEL BUFFERED SERIAL PORTS SIGNALS
CLKR0
I/O/Z
McBSP0 receive clock. CLKR0 serves as the serial shift clock for the serial
port receiver. At reset, this pin is in high-impedance mode.
H
Hi-Z
DR0
I
McBSP0 receive data
FS
Input
FSR0
I/O/Z
McBSP0 receive frame synchronization. The FSR0 pulse initiates the data
receive process over DR0. At reset, this pin is in high-impedance mode.
Hi-Z
CLKX0
I/O/Z
McBSP0 transmit clock. CLKX0 serves as the serial shift clock for the
serial port transmitter. The CLKX0 pin is configured as input after reset.
H
Input
DX0
O/Z
McBSP0 transmit data. DX0 is placed in the high-impedance state when
not transmitting, when RESET is asserted, or when OFF is low.
Hi-Z
FSX0
I/O/Z
McBSP0 transmit frame synchronization. The FSX0 pulse initiates the
data transmit process over DX0. Configured as an input following reset.
Input
S10
I/O/Z
McBSP1
command/response. At reset, this pin is configured as McBSP1.CLKR.
receive
clock
or
MultiMedia
Card/Secure
Digital1
McBSP1.CLKR
I/Z
McBSP1 receive clock. McBSP1.CLKR serves as the serial shift clock for
the serial port receiver. McBSP1.CLKR is selected when the External Bus
Selection Register has 00 in the Serial Port1 Mode bit field or following
reset.
H
Input
MMC1.CMD
SD1.CMD
I/O/Z
MMC1 or SD1 command/response is selected when the External Bus
Selection Register has 10 in the Serial Port1 Mode bit field.
S11
I/O/Z
McBSP1 data receive or Secure Digital1 data1. At reset, this pin is
configured as McBSP1.DR.
McBSP1.DR
I/Z
McBSP1 serial data receive. McBSP1.DR is selected when the External
Bus Selection Register has 00 in the Serial Port1 Mode bit field or following
reset.
Input
SD1.DAT1
I/O/Z
SD1 data1 is selected when the External Bus Selection Register has 10 in
the Serial Port1 Mode bit field.
I = Input, O = Output, S = Supply, Hi-Z = High-impedance
BK = bus keeper (the bus keeper maintains the previous voltage level during reset or while the output pin is not driven), PU = pullup,
PD = pulldown, H = hysteresis input buffer, FS = fail-safe buffer
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參數(shù)描述
TMX320VC5509APGE 制造商:Texas Instruments 功能描述:
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