參數(shù)資料
型號： TMX320VC5509AGHH
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： TMS320VC5509A Fixed-Point Digital Signal Processor
中文描述： TMS320VC5509A定點(diǎn)數(shù)字信號處理器
文件頁數(shù)： 116/144頁
文件大?。?/td> 1603K
代理商： TMX320VC5509AGHH
Electrical Specifications
116
November 2002 Revised January 2005
SPRS205D
5.14.3
McBSP as SPI Master or Slave Timings
Table 527 to Table 534 assume testing over recommended operating conditions (see Figure 526 through
Figure 529).
Table 527. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)
NO.
CV
DD
= 1.2 V
CV
DD
= 1.35 V
MASTER
MIN
MAX
CV
DD
= 1.6 V
UNIT
SLAVE
MIN
MASTER
MIN
SLAVE
MIN
MAX
MAX
MAX
MC23
t
su(DRV-CKXL)
Setup time, DR valid before
CLKX low
15
3 6P
10
3 6P
ns
MC24
t
h(CKXL-DRV)
Hold time, DR valid after
CLKX low
0
3 + 6P
0
3 + 6P
ns
MC25
t
su(FXL-CKXH)
Setup time, FSX low before
CLKX high
5
5
ns
MC26
t
c(CKX)
Cycle time, CLKX
2P
16P
2P
16P
ns
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
P = 1/CPU clock frequency. For example, when running parts at 200 MHz, use P = 5 ns. In addition to CPU frequency, the maximum operating
frequency of the serial port also depends on meeting the rest of the switching characteristics and timing requirements parameters specified.
Table 528. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)
NO.
PARAMETER
CV
DD
= 1.2 V
CV
DD
= 1.35 V
CV
DD
= 1.6 V
UNIT
MASTER
§
MIN
SLAVE
MIN
MASTER
§
MIN
SLAVE
MIN
MAX
MAX
MAX
MAX
MC27
t
d(CKXL-FXL)
Delay time, CLKX low
to FSX low
T 5
T + 5
T 4
T + 4
ns
MC28
t
d(FXL-CKXH)
Delay time, FSX low to
CLKX high
#
C 5
C + 5
C 4
C + 4
ns
MC29
t
d(CKXH-DXV)
Delay time, CLKX high
to DX valid
4
6
3P + 3
5P + 15
3
3
3P + 3
5P + 8
ns
MC30
t
dis(CKXL-DXHZ)
Disable time, DX high-
impedance
last data bit from CLKX
low
following
C 4
C + 4
C 3
C + 1
ns
MC31
t
dis(FXH-DXHZ)
Disable time, DX high-
impedance
last data bit from FSX
high
following
3P+ 4
3P + 19
3P+ 3
3P + 11
ns
MC32
t
d(FXL-DXV)
Delay time, FSX low to
DX valid
3P + 4
3P + 18
3P + 4
3P + 10
ns
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
P = 1/CPU clock frequency. For example, when running parts at 200 MHz, use P = 5 ns. In addition to CPU frequency, the maximum operating
frequency of the serial port also depends on meeting the rest of the switching characteristics and timing requirements parameters specified.
§
T =
CLKX period = (1 + CLKGDV) * 2P
C =
CLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2P when CLKGDV is even
FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
#
FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
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