參數(shù)資料
型號： TMX320VC5509AGHH
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： TMS320VC5509A Fixed-Point Digital Signal Processor
中文描述： TMS320VC5509A定點(diǎn)數(shù)字信號處理器
文件頁數(shù)： 66/144頁
文件大?。?/td> 1603K
代理商： TMX320VC5509AGHH
Functional Overview
66
November 2002 Revised January 2005
SPRS205D
Table 330. Multichannel Serial Port #2
PORT ADDRESS
(WORD)
REGISTER NAME
DESCRIPTION
RESET VALUE
0x3000
DRR2_2[15:0]
Data Receive Register 2, McBSP #2
0000 0000 0000 0000
0x3001
DRR1_2[15:0]
Data Receive Register 1, McBSP #2
0000 0000 0000 0000
0x3002
DXR2_2[15:0]
Data Transmit Register 2, McBSP #2
0000 0000 0000 0000
0x3003
DXR1_2[15:0]
Data Transmit Register 1, McBSP #2
0000 0000 0000 0000
0x3004
SPCR2_2[15:0]
Serial Port Control Register 2, McBSP #2
0000 0000 0000 0000
0x3005
SPCR1_2[15:0]
Serial Port Control Register 1, McBSP #2
0000 0000 0000 0000
0x3006
RCR2_2[15:0]
Receive Control Register 2, McBSP #2
0000 0000 0000 0000
0x3007
RCR1_2[15:0]
Receive Control Register 1, McBSP #2
0000 0000 0000 0000
0x3008
XCR2_2[15:0]
Transmit Control Register 2, McBSP #2
0000 0000 0000 0000
0x3009
XCR1_2[15:0]
Transmit Control Register 1, McBSP #2
0000 0000 0000 0000
0x300A
SRGR2_2[15:0]
Sample Rate Generator Register 2, McBSP #2
0020 0000 0000 0000
0x300B
SRGR1_2[15:0]
Sample Rate Generator Register 1, McBSP #2
0000 0000 0000 0001
0x300C
MCR2_2[15:0]
Multichannel Control Register 2, McBSP #2
0000 0000 0000 0000
0x300D
MCR1_2[15:0]
Multichannel Control Register 1, McBSP #2
0000 0000 0000 0000
0x300E
RCERA_2[15:0]
Receive Channel Enable Register Partition A, McBSP #2
0000 0000 0000 0000
0x300F
RCERB_2[15:0]
Receive Channel Enable Register Partition B, McBSP #2
0000 0000 0000 0000
0x3010
XCERA_2[15:0]
Transmit Channel Enable Register Partition A, McBSP #2
0000 0000 0000 0000
0x3011
XCERB_2[15:0]
Transmit Channel Enable Register Partition B, McBSP #2
0000 0000 0000 0000
0x3012
PCR2[15:0]
Pin Control Register, McBSP #2
0000 0000 0000 0000
0x3013
RCERC_2[15:0]
Receive Channel Enable Register Partition C, McBSP #2
0000 0000 0000 0000
0x3014
RCERD_2[15:0]
Receive Channel Enable Register Partition D, McBSP #2
0000 0000 0000 0000
0x3015
XCERC_2[15:0]
Transmit Channel Enable Register Partition C, McBSP #2
0000 0000 0000 0000
0x3016
XCERD_2[15:0]
Transmit Channel Enable Register Partition D, McBSP #2
0000 0000 0000 0000
0x3017
RCERE_2[15:0]
Receive Channel Enable Register Partition E, McBSP #2
0000 0000 0000 0000
0x3018
RCERF_2[15:0]
Receive Channel Enable Register Partition F, McBSP #2
0000 0000 0000 0000
0x3019
XCERE_2[15:0]
Transmit Channel Enable Register Partition E, McBSP #2
0000 0000 0000 0000
0x301A
XCERF_2[15:0]
Transmit Channel Enable Register Partition F, McBSP #2
0000 0000 0000 0000
0x301B
RCERG_2[15:0]
Receive Channel Enable Register Partition G, McBSP #2
0000 0000 0000 0000
0x301C
RCERH_2[15:0]
Receive Channel Enable Register Partition H, McBSP #2
0000 0000 0000 0000
0x301D
XCERG_2[15:0]
Transmit Channel Enable Register Partition G, McBSP #2
0000 0000 0000 0000
0x301E
XCERH_2[15:0]
Transmit Channel Enable Register Partition H, McBSP #2
0000 0000 0000 0000
Hardware reset; x denotes a “don’t care.”
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