參數(shù)資料
型號： TMX320VC5509AGHH
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： TMS320VC5509A Fixed-Point Digital Signal Processor
中文描述： TMS320VC5509A定點(diǎn)數(shù)字信號處理器
文件頁數(shù)： 56/144頁
文件大?。?/td> 1603K
代理商： TMX320VC5509AGHH
Functional Overview
56
November 2002 Revised January 2005
SPRS205D
3.10 Peripheral Register Description
Each 5509A device has a set of memory-mapped registers associated with peripherals as listed in Table 322
through Table 339. Some registers use less than 16 bits. When reading these registers, unused bits are
always read as 0.
NOTE:
The CPU access latency to the peripheral memory-mapped registers is 6 CPU cycles.
Following peripheral register update(s), the CPU must wait at least 6 CPU cycles before
attempting to use that peripheral. When more than one peripheral register is updated in a
sequence, the CPU only needs to wait following the final register write. For example, if the
EMIF is being reconfigured, the CPU must wait until the very last EMIF register update takes
effect before trying to access the external memory. The users should consult the respective
peripheral user’s guide to determine if a peripheral requires additional time to initialize itself
to the new configuration after the register updates take effect.
Before reading or writing to the USB register, the USB module has to be brought out of reset by setting bit 2
of the USB Idle Control and Status Register. Likewise, the MMC/SD must be selected by programming the
External Bus Selection Register before reading or writing the MMC/SD module registers.
Table 322. Idle Control, Status, and System Registers
WORD ADDRESS
REGISTER NAME
DESCRIPTION
RESET VALUE
0x0001
ICR[7:0]
Idle Control Register
xxxx xxxx 0000 0000
0x0002
ISTR[7:0]
Idle Status Register
xxxx xxxx 0000 0000
0x07FD
SYSR[15:0]
System Register
0000 0000 0000 0000
Hardware reset; x denotes a “don’t care.”
Table 323. External Memory Interface Registers
WORD ADDRESS
REGISTER NAME
DESCRIPTION
RESET VALUE
0x0800
EGCR[15:0]
EMIF Global Control Register
xxxx xxxx 0010 xx00
0x0801
EMI_RST
EMIF Global Reset Register
xxxx xxxx xxxx xxxx
0x0802
EMI_BE[13:0]
EMIF Bus Error Status Register
xx00 0000 0000 0000
0x0803
CE0_1[14:0]
EMIF CE0 Space Control Register 1
x010 1111 1111 1111
0x0804
CE0_2[15:0]
EMIF CE0 Space Control Register 2
0100 1111 1111 1111
0x0805
CE0_3[7:0]
EMIF CE0 Space Control Register 3
xxxx xxxx 0000 0000
0x0806
CE1_1[14:0]
EMIF CE1 Space Control Register 1
x010 1111 1111 1111
0x0807
CE1_2[15:0]
EMIF CE1 Space Control Register 2
0100 1111 1111 1111
0x0808
CE1_3[7:0]
EMIF CE1 Space Control Register 3
xxxx xxxx 0000 0000
0x0809
CE2_1[14:0]
EMIF CE2 Space Control Register 1
x010 1111 1111 1111
0x080A
CE2_2[15:0]
EMIF CE2 Space Control Register 2
0101 1111 1111 1111
0x080B
CE2_3[7:0]
EMIF CE2 Space Control Register 3
xxxx xxxx 0000 0000
0x080C
CE3_1[14:0]
EMIF CE3 Space Control Register 1
x010 1111 1111 1111
0x080D
CE3_2[15:0]
EMIF CE3 Space Control Register 2
0101 1111 1111 1111
0x080E
CE3_3[7:0]
EMIF CE3 Space Control Register 3
xxxx xxxx 0000 0000
0x080F
SDC1[15:0]
EMIF SDRAM Control Register 1
1111 1001 0100 1000
0x0810
SDPER[11:0]
EMIF SDRAM Period Register
xxxx 0000 1000 0000
0x0811
SDCNT[11:0]
EMIF SDRAM Counter Register
xxxx 0000 1000 0000
0x0812
INIT
EMIF SDRAM Init Register
xxxx xxxx xxxx xxxx
0x0813
SDC2[9:0]
EMIF SDRAM Control Register 2
xxxx xx11 1111 1111
0x0814
Hardware reset; x denotes a “don’t care.”
SDC3
EMIF SDRAM Control Register 3
0000 0000 0000 0111
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