參數(shù)資料
型號： TMX320VC5509AGHH
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： TMS320VC5509A Fixed-Point Digital Signal Processor
中文描述： TMS320VC5509A定點數(shù)字信號處理器
文件頁數(shù)： 112/144頁
文件大?。?/td> 1603K
代理商： TMX320VC5509AGHH
Electrical Specifications
112
November 2002 Revised January 2005
SPRS205D
Table 524. McBSP0 Switching Characteristics
NO.
PARAMETER
CV
DD
= 1.2 V
CV
DD
= 1.35 V
MIN
CV
DD
= 1.6 V
UNIT
MAX
MIN
MAX
MC1
t
c(CKRX)
t
r(CKRX)
t
f(CKRX)
t
w(CKRXH)
t
w(CKRXL)
Cycle time, CLKR/X
CLKR/X int
2P
2P
ns
MC3
Rise time, CLKR/X
CLKR/X int
1
1
ns
MC4
Fall time, CLKR/X
CLKR/X int
1
1
ns
MC11
Pulse duration, CLKR/X high
CLKR/X int
D2
§
C2
§
D+2
§
C+2
§
D1
§
C1
§
D+1
§
C+1
§
ns
MC12
Pulse duration, CLKR/X low
CLKR/X int
ns
MC13
t
d(CKRH-FRV)
Delay time, CLKR high to internal FSR valid
CLKR int
2
1
2
1
ns
CLKR ext
4
13
4
8
MC14
t
d(CKXH-FXV)
Delay time, CLKX high to internal FSX valid
CLKX int
2
2
2
2
ns
CLKX ext
4
15
4
9
MC15
t
dis(CKXH-DXHZ)
Disable time, DX high-impedance from CLKX high
following last data bit
CLKX int
0
5
5
1
ns
CLKX ext
10
18
3
11
Delay time, CLKX high to DX valid.
This applies to all bits except the first bit
transmitted.
CLKX int
5
4
CLKX ext
15
9
MC16
t
d(CKXH-DXV)
Delay time, CLKX high to DX
valid
DXENA = 0
CLKX int
4
2
ns
Only
1 or 2 (XDATDLY = 01b or 10b)
modes
applies
to
first
bit
CLKX ext
13
7
DXENA = 1
CLKX int
2P + 1
2P + 1
transmitted when in Data Delay
CLKX ext
2P + 4
2P + 3
Enable time, DX driven from
CLKX high
DXENA = 0
CLKX int
1
3
MC17
t
en(CKXH-DX)
Only
1 or 2 (XDATDLY= 01b or 10b)
modes
applies
to
first
bit
CLKX ext
6
3
ns
DXENA = 1
CLKX int
P 1
P 3
transmitted when in Data Delay
CLKX ext
P + 6
P + 3
Delay time, FSX high to DX
valid
DXENA = 0
FSX int
2
2
MC18
t
d(FXH-DXV)
FSX ext
13
8
ns
Only
transmitted when in Data Delay
0 (XDATDLY= 00b) mode.
Enable time, DX driven from
FSX high
applies
to
first
bit
DXENA = 1
FSX int
2P + 1
2P + 1
FSX ext
2P + 10
2P + 10
DXENA = 0
FSX int
0
0
MC19
t
en(FXH-DX)
FSX ext
8
3
ns
Only
transmitted when in Data Delay
0 (XDATDLY= 00b) mode
applies
to
first
bit
DXENA = 1
FSX int
P 3
P 3
FSX ext
P + 8
P + 4
Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of
that signal are
also inverted.
P = 1/CPU clock frequency. For example, when running parts at 200 MHz, use P = 5 ns. In addition to CPU frequency, the maximum operating
frequency of the serial port also depends on meeting the rest of the switching characteristics and timing requirements parameters specified.
§
T=CLKRX period = (1 + CLKGDV) * P
C=CLKRX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * P when CLKGDV is even
D=CLKRX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * P when CLKGDV is even
See the
TMS320C55x DSP Peripherals Overview Reference Guide
(literature number SPRU317) for a description of the DX enable (DXENA)
and data delay features of the McBSP.
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