參數(shù)資料
型號： TMX320VC5509AGHH
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： TMS320VC5509A Fixed-Point Digital Signal Processor
中文描述： TMS320VC5509A定點(diǎn)數(shù)字信號處理器
文件頁數(shù)： 29/144頁
文件大?。?/td> 1603K
代理商： TMX320VC5509AGHH
Introduction
29
November 2002 Revised January 2005
SPRS205D
Table 23. Signal Descriptions (Continued)
TERMINAL
NAME
RESET
CONDITION
BK
FUNCTION
I/O/Z
MULTIPLEXED
SIGNAL NAME
USB
DP
I/O/Z
Differential (positive) receive/transmit. At reset, this pin is configured as
input.
Input
DN
I/O/Z
Differential (negative) receive/transmit. At reset, this pin is configured as
input.
Input
PU
O/Z
Pullup output. This pin is used to pull up the detection resistor required by
the USB specification. The pin is internally connected to USBV
DD
via a
software controllable switch (CONN bit of the USBCTL register).
Hi-Z
A/D
AIN0
I
Analog Input Channel 0
Input
AIN1
I
Analog Input Channel 1
Input
AIN2 (BGA only)
I
Analog Input Channel 2. (BGA package only)
Input
AIN3 (BGA only)
I
Analog Input Channel 3. (BGA package only)
Input
TEST/EMULATION PINS
TCK
I
IEEE standard 1149.1 test clock. TCK is normally a free-running clock
signal with a 50% duty cycle. The changes on test access port (TAP) of
input signals TMS and TDI are clocked into the TAP controller, instruction
register, or selected test data register on the rising edge of TCK. Changes
at the TAP output signal (TDO) occur on the falling edge of TCK.
PU
H
Input
TDI
I
IEEE standard 1149.1 test data input. Pin with internal pullup device. TDI is
clocked into the selected register (instruction or data) on a rising edge of
TCK.
PU
Input
TDO
O/Z
IEEE standard 1149.1 test data output. The contents of the selected
register (instruction or data) are shifted out of TDO on the falling edge of
TCK. TDO is in the high-impedance state except when the scanning of
data is in progress.
Hi-Z
TMS
I
IEEE standard 1149.1 test mode select. Pin with internal pullup device.
This serial control input is clocked into the TAP controller on the rising edge
of TCK.
PU
Input
TRST
I
IEEE standard 1149.1 test reset. TRST, when high, gives the IEEE
standard 1149.1 scan system control of the operations of the device. If
TRST is not connected or driven low, the device operates in its functional
mode, and the IEEE standard 1149.1 signals are ignored. This pin has an
internal pulldown.
PD
FS
Input
EMU0
I/O/Z
Emulator 0 pin. When TRST is driven low, EMU0 must be high for
activation of the OFF condition. When TRST is driven high, EMU0 is used
as an interrupt to or from the emulator system and is defined as I/O by way
of the IEEE standard 1149.1 scan system.
PU
Input
I = Input, O = Output, S = Supply, Hi-Z = High-impedance
BK = bus keeper (the bus keeper maintains the previous voltage level during reset or while the output pin is not driven), PU = pullup,
PD = pulldown, H = hysteresis input buffer, FS = fail-safe buffer
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