參數(shù)資料
型號: TMX320VC5509AGHH
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號處理
英文描述: TMS320VC5509A Fixed-Point Digital Signal Processor
中文描述: TMS320VC5509A定點數(shù)字信號處理器
文件頁數(shù): 35/144頁
文件大小: 1603K
代理商: TMX320VC5509AGHH
Functional Overview
35
November 2002 Revised January 2005
SPRS205D
3.1.4.2
GHH and ZHH Package Memory Map
The GHH and ZHH packages feature 21 address bits representing 2M-byte linear address for asynchronous
memories per CE space. Due to address row/column multiplexing, address reach for SDRAM devices is
4M bytes for each CE space. The largest SDRAM device that can be used with the 5509A in a GHH or ZHH
package is 128M-bit SDRAM.
Byte Address
(Hex)
Memory Blocks
000000
DARAM / HPI Access
(32K 192) Bytes
008000
DARAM
32K Bytes
010000
SARAM
§
192K Bytes
External
CE0
040000
400000
800000
C00000
FF0000
FF8000
32K Bytes
FFC000
16K Bytes
16K Bytes
FFFFFF
External
CE1
External
CE2
External
CE3
Block Size
(if MPNMC=0)
ROM
||
(if MPNMC=0)
ROM
||
(if MPNMC=1)
External
CE3
(if MPNMC=1)
External
CE3
(if MPNMC=1)
External
CE3
2M Bytes Asynchronous
4M Bytes SDRAM (MPNMC = 1)
4M Bytes 64K Bytes if internal ROM selected (MPNMC = 0)
2M Bytes Asynchronous
4M Bytes SDRAM
2M Bytes Asynchronous
4M Bytes SDRAM
2M Bytes Asynchronous
4M Bytes 256K Bytes SDRAM
#
Address shown represents the first byte address in each block.
Dual-access RAM (DARAM): two accesses per cycle per block, 8 blocks of 8K bytes.
§
Single-access RAM (SARAM): one access per cycle per block, 24 blocks of 8K bytes.
External memory spaces are selected by the chip-enable signal shown (CE[0:3]). Supported memory types include: asynchronous static
RAM (SRAM) and synchronous DRAM (SDRAM).
#
The minus 256K bytes consists of 32K-byte DARAM/HPI access, 32K-byte DARAM, and 192K-byte SARAM.
||
Read-only memory (ROM): one access every two cycles, two blocks of 32K bytes.
0000C0
MMR (Reserved)
Figure 33. TMS320VC5509A Memory Map (GHH and ZHH Packages)
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