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參數(shù)資料
| 型號(hào)： | TMX320VC5509AGHH |
| 廠商： | Texas Instruments, Inc. |
| 元件分類(lèi)： | 數(shù)字信號(hào)處理 |
| 英文描述： | TMS320VC5509A Fixed-Point Digital Signal Processor |
| 中文描述： | TMS320VC5509A定點(diǎn)數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 33/144頁(yè) |
| 文件大?。?/td> | 1603K |
| 代理商： | TMX320VC5509AGHH |
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Functional Overview
33
November 2002 Revised January 2005
SPRS205D
3.1.3 On-Chip Read-Only Memory (ROM)
The one-wait-state ROM is located at the byte address range FF0000hFFFFFFh. The ROM is composed
of one block of 32K bytes and two 16K-byte blocks, for a total of 64K bytes of ROM. The ROM address space
can be mapped by software to the external memory or to the internal ROM.
NOTE:
Customers can arrange to have the 5509A ROM programmed with contents unique
to any particular application. Contact your local Texas Instruments representative for more
information on custom ROM programming.
The standard 5509A device includes a bootloader program resident in the ROM. When the MPNMC bit field
of the ST3 status register is set through software, the on-chip ROM is disabled and not present in the memory
map, and byte address range FF0000hFFFFFFh is directed to external memory space. A hardware reset
always clears the MPNMC bit, so it is not possible to disable the ROM at reset. However, the software reset
instruction does not affect the MPNMC bit. All three ROM blocks can be accessed by the program, data, or
DMA buses. The first 16-bit word access to ROM requires three cycles. Subsequent accesses require two
cycles per 16-bit word.
3.1.4 Memory Map
The 5509A provides 16M bytes of total memory space composed of on-chip RAM, on-chip ROM, and external
memory space supporting a variety of memory types. The on-chip, dual-access RAM allows two accesses
to a given block during the same cycle. The 5509A supports 8 blocks of 8K bytes of dual-access RAM. The
on-chip, single-access RAM allows one access to a given block per clock cycle. The 5509A supports
24 blocks of 8K byte of single-access RAM.
The remainder of the memory map is external space that is divided into four spaces. Each space has a chip
enable decode signal (called CE) that indicates an access to the selected space. The External Memory
Interface (EMIF) supports access to asynchronous memories such as SRAM and Flash, and synchronous
DRAM.
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