參數(shù)資料
型號： TMX320VC5509AGHH
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： TMS320VC5509A Fixed-Point Digital Signal Processor
中文描述： TMS320VC5509A定點數(shù)字信號處理器
文件頁數(shù)： 42/144頁
文件大小： 1603K
代理商： TMX320VC5509AGHH
Functional Overview
42
November 2002 Revised January 2005
SPRS205D
3.5.2 Parallel Port
The parallel port of the 5509A consists of 14 (LQFP) or 21 (BGA) address signals, 16 data signals, and 15
control signals. Its 14 bits for address allow it to access 16K (LQFP) or 2M bytes of external memory when
using the asynchronous SRAM interface. On the other hand, the SDRAM interface can access the whole
external memory space of 16M bytes. The parallel bus supports four different modes:
Full EMIF mode:
the EMIF with its 14 (LQFP) or 21 address signals, 16 data signals, and 15 control
signals routed to the corresponding external parallel bus address, data, and control signals.
Data EMIF mode:
the EMIF with its 16 data signals, and 15 control signals routed to the corresponding
external parallel bus data and control signals. The 14 (LQFP) or 16 (BGA) address bus signals can be
used as general-purpose I/O signals only.
Non-multiplexed HPI mode:
the HPI is enabled with its 14 address signals, 16 data signals, and
8 control signals routed to the corresponding address, data, and control signals of the external parallel
bus. Moreover, 7 control signals of the external parallel bus are used as general-purpose I/O.
Multiplexed HPI mode:
the HPI is enabled with its 16 data signals and 10 control signals routed to the
external parallel bus. In addition, 5 control signals of the external parallel bus are used as general-purpose
I/O. The external parallel port’s 14 (LQFP) or 16 (BGA) address signals are used as general-purpose I/O.
Table 36. TMS320VC5509A Parallel Port Signal Routing
Pin Signal
Data EMIF (00)
Full EMIF (01)
Non-Multiplex HPI (10)
Multiplex HPI (11)
Address Bus
A’[0]
N/A
EMIF.A[0] (BGA)
EMIF.A[0] (LQFP)
N/A
N/A
A[0]
GPIO.A[0] (LQFP)
GPIO.A[0] (BGA)
GPIO.A[13:1] (LQFP)
GPIO.A[13:1] (BGA)
GPIO.A[15:14] (BGA)
N/A
HPI.HA[0] (LQFP)
HPI.HA[0] (BGA)
HPI.HA[13:1] (LQFP)
HPI.HA[13:1] (BGA)
N/A
N/A
GPIO.A[0] (LQFP)
GPIO.A[0] (BGA)
GPIO.A[13:1] (LQFP)
GPIO.A[13:1] (BGA)
GPIO.A[15:14] (BGA)
N/A
A[13:1]
EMIF.A[13:1] (LQFP)
EMIF.A[13:1] (BGA)
EMIF.A[15:14] (BGA)
EMIF.A[20:16] (BGA)
A[15:14]
A[20:16]
Data Bus
D[15:0]
EMIF.D[15:0]
EMIF.D[15:0]
HPI.HD[15:0]
HPI.HD[15:0]
Control Bus
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
EMIF.ARE
EMIF.AOE
EMIF.AWE
EMIF.ARDY
EMIF.CE0
EMIF.CE1
EMIF.CE2
EMIF.CE3
EMIF.BE0
EMIF.BE1
EMIF.SDRAS
EMIF.SDCAS
EMIF.SDWE
EMIF.SDA10
EMIF.CLKMEM
EMIF.ARE
EMIF.AOE
EMIF.AWE
EMIF.ARDY
EMIF.CE0
EMIF.CE1
EMIF.CE2
EMIF.CE3
EMIF.BE0
EMIF.BE1
EMIF.SDRAS
EMIF.SDCAS
EMIF.SDWE
EMIF.SDA10
EMIF.CLKMEM
GPIO8
HPI.HINT
HPI.HR/W
HPI.HRDY
GPIO9
GPIO10
HPI.HCNTL0
GPIO11
HPI.HBE0
HPI.HBE1
GPIO12
HPI.HCS
HPI.HDS1
GPIO13
HPI.HDS2
GPIO8
HPI.HINT
HPI.HR/W
HPI.HRDY
GPIO9
GPIO10
HPI.HCNTL0
HPI.HCNTL1
HPI.HBE0
HPI.HBE1
HPI.HAS
HPI.HCS
HPI.HDS1
GPIO13
HPI.HDS2
Represents the Parallel Port Mode bits of the External Bus Selection Register.
A[20:16] of the BGA package always functions as EMIF address pins and they cannot be reconfigured for any other function.
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