參數(shù)資料
型號： TMX320VC5509AGHH
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： TMS320VC5509A Fixed-Point Digital Signal Processor
中文描述： TMS320VC5509A定點數(shù)字信號處理器
文件頁數(shù)： 90/144頁
文件大?。?/td> 1603K
代理商： TMX320VC5509AGHH
Electrical Specifications
90
November 2002 Revised January 2005
SPRS205D
5.6.3 Clock Generation in Bypass Mode (DPLL Disabled)
The frequency of the reference clock provided at the X2/CLKIN pin can be divided by a factor of one, two, or
four to generate the internal CPU clock cycle. The divide factor (D) is set in the BYPASS_DIV field of the clock
mode register. The contents of this field only affect clock generation while the device is in bypass mode. In
this mode, the digital phase-locked loop (DPLL) clock synthesis is disabled.
Table 52 and Table 53 assume testing over recommended operating conditions and H = 0.5t
c(CO)
(see
Figure 53).
Table 52. CLKIN Timing Requirements
NO.
CV
DD
= 1.2 V
CV
DD
= 1.35 V
CV
DD
= 1.6 V
MIN
UNIT
MAX
400
C1
t
c(CI)
t
f(CI)
t
r(CI)
t
w(CIL)
t
w(CIH)
Cycle time, X2/CLKIN
20
ns
C2
Fall time, X2/CLKIN
4
ns
C3
Rise time, X2/CLKIN
4
ns
C10
Pulse duration, CLKIN low
6
ns
C11
Pulse duration, CLKIN high
6
ns
This device utilizes a fully static design and therefore can operate with t
c(CI)
approaching
∞
. If an external crystal is used, the X2/CLKIN cycle
time is limited by the crystal frequency range listed in Table 51.
Table 53. CLKOUT Switching Characteristics
NO.
PARAMETER
CV
DD
= 1.2 V
CV
DD
= 1.35 V
CV
DD
= 1.6 V
UNIT
MIN
20
TYP
MAX
1600
C4
t
c(CO)
t
d(CI-CO)
t
f(CO)
t
r(CO)
t
w(COL)
t
w(COH)
Cycle time, CLKOUT
D*t
c(CI)§
15
ns
C5
Delay time, X2/CLKIN high to CLKOUT high/low
5
25
ns
C6
Fall time, CLKOUT
1
ns
C7
Rise time, CLKOUT
1
ns
C8
Pulse duration, CLKOUT low
H 1
H + 1
ns
C9
Pulse duration, CLKOUT high
H 1
H + 1
ns
This device utilizes a fully static design and therefore can operate with t
c(CO)
approaching
∞
. If an external crystal is used, the X2/CLKIN cycle
time is limited by the crystal frequency range listed in Table 51.
It is recommended that the DPLL synthesised clocking option be used to obtain maximum operating frequency.
§
D = 1/(PLL Bypass Divider)
C3
C2
C1
C4
C5
C7
C6
C8
C9
X2/CLKIN
CLKOUT
C10
C11
NOTE A: The relationship of X2/CLKIN to CLKOUT depends on the PLL bypass divide factor chosen for the CLKMD register. The waveform
relationship shown in Figure 53 is intended to illustrate the timing parameters based on CLKOUT = 1/2(CLKIN) configuration.
Figure 53. Bypass Mode Clock Timings
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