
- 48 -
8-3-29. RIRQ register
Enables event interruption cause.
Bits set to 1 that will enable an event interrupt for that event.
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Bit name
IREN
IRN
IRNM
IRND
IRUS
IRUE
IRDS
IRDE
IRC1
IRC2
IRC3
IRC4
IRC5
IRCL
IRLT
IROL
IRSD
IRDR
IRSA
Not defined (Always set to 0.)
Description
Stopping normally.
Starting the next operation continuously.
Writing to the 2nd pre-register.
Writing to the 2nd pre-register for Comparator 5.
Starting acceleration.
When ending acceleration.
When starting deceleration.
When ending deceleration.
When Comparator 1 conditions are met.
When Comparator 2 conditions are met.
When Comparator 3 conditions are met.
When Comparator 4 conditions are met.
When Comparator 5 conditions are met.
When resetting the count value with a CLR signal input.
When latching the count value with an LTC signal input.
When latching the count value with an ORG signal input.
When the SD input is ON.
When the ±DR input is changed.
When the
input is ON.
19 to 31
8-3-30. RLTC1 register
Latched data for COUNTER1 (command position). (Read only.)
The contents of COUNTER1 are copied when triggered by the LTC, an ORG input, or an LTCH
command.
Data range: -134,217,728 to +134,217,727.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
&
&
&
&
8-3-31. RLTC2 register
Latched data for COUNTER2 (mechanical position). (Read only.)
The contents of COUNTER2 are copied when triggered by the LTC, an ORG input, or an LTCH
command.
Data range: -134,217,728 to +134,217,727.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IROL
IRLT
IRCL
IRC5
IRC4
IRC3
IRC2
IRC1
IRDE
IRDS
IRUE
IRUS
IRND
IRNM
IRN
IREN
0
0
0
0
0
0
0
0
0
0
0
0
0
IRSA
IRDR
IRSD
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
&
&
&
&