參數(shù)資料
型號： PCL6045B
廠商： Electronic Theatre Controls, Inc.
英文描述： User Manual For PCL6045B Pulse Control LSI
中文描述： 用戶手冊PCL6045B脈沖控制大規(guī)模集成電路
文件頁數(shù)： 144/176頁
文件大?。?/td> 7952K
代理商： PCL6045B
-
137
-
[Error
interrupt
causes]
<Detail
of
REST:
The
cause
of
an
interrupt
makes
the
corresponding
bit
"1">
Cause
(REST)
Error
interrupt
cause
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
Bit
name
ESC1
ESC2
ESC3
ESC4
ESC5
ESPL
ESML
ESAL
ESSP
ESEM
ESSD
Not
defined
ESDT
Stopped
by
Comparator
1
conditions
being
satisfied
(+SL)
Stopped
by
Comparator
2
conditions
being
satisfied
(-SL)
Stopped
by
Comparator
3
conditions
being
satisfied
Stopped
by
Comparator
4
conditions
being
satisfied
Stopped
by
Comparator
5
conditions
being
satisfied
Stopped
by
turning
ON
the
+EL
input
Stopped
by
turning
ON
the
-EL
input
Stopped
by
turning
ON
the
ALM
input
Stopped
by
turning
ON
the
Stopped
by
turning
ON
the
Deceleration
stopped
by
turning
ON
the
SD
input
(Always
0)
Stopped
by
an
operation
data
error.
Simultaneously
stopped
with
another
axis
due
to
an
error
stop
on
the
other
axis
during
an
interpolation
operation
Stopped
by
an
overflow
of
PA/PB
input
buffer
counter
occurrence
Stopped
by
an
over
range
count
occurrence
while
positioning
in
an
interpolation
operation
An
EA/EB
input
error
occurred
(does
not
stop).
An
PA/PB
input
error
occurred
(does
not
stop).
input
input
13
ESIP
14
15
ESPO
ESAO
16
17
ESEE
ESPE
[Event
interrupt
causes]
<
The
corresponding
interrupt
bit
is
set
to
1
and
then
an
interrupt
occurred>
Set
cause
(RIRQ) Cause
(RIST)
Bit
Bit
name
0
IREN
1
IRNX
2
IRNM
3
IRND
Event
interrupt
cause
Bit
0
1
2
3
Bit
name
ISEN
ISNX
ISNM
ISND
Automatic
stop
The
next
operation
starts
continuously
When
it
is
possible
to
write
an
operation
to
the
2nd
pre-register
When
it
is
possible
to
write
to
the
2nd
pre-register
for
Comparator
5
When
acceleration
starts
When
acceleration
ends
When
deceleration
starts
When
deceleration
ends
When
the
Comparator
1
conditions
are
satisfied
When
the
Comparator
2
conditions
are
satisfied
When
the
Comparator
3
conditions
are
satisfied
When
the
Comparator
4
conditions
are
satisfied
When
the
Comparator
5
conditions
are
satisfied
When
the
counter
value
is
reset
by
a
CLR
signal
input
When
the
counter
value
is
latched
by
an
LTC
input
When
the
counter
value
is
latched
by
an
ORG
input
When
the
SD
input
is
turned
ON
When
the
+DR
input
changes
When
the
-DR
input
changes
When
the
input
is
turned
ON
4
5
6
7
8
9
10
11
12
13
14
15
16
IRUS
IRUE
IRDS
IRDE
IRC1
IRC2
IRC3
IRC4
IRC5
IRCL
IRLT
IROL
IRSD
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
ISUS
ISUE
ISDS
ISDE
ISC1
ISC2
ISC3
ISC4
ISC5
ISCL
ISLT
ISOL
ISSD
ISPD
ISMD
ISSA
17
IRDR
18
IRSA
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