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參數(shù)資料
| 型號(hào)： | PCL6045B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | User Manual For PCL6045B Pulse Control LSI |
| 中文描述： | 用戶手冊(cè)PCL6045B脈沖控制大規(guī)模集成電路 |
| 文件頁(yè)數(shù)： | 112/176頁(yè) |
| 文件大小： | 7952K |
| 代理商： | PCL6045B |
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-
105
-
11-5-3.
ORG,
EZ
signals
These
signals
are
enabled
in
the
zero
return
modes
(zero
return,
leave
zero
position,
and
zero
position
search)
and
in
the
EZ
count
operation
modes.
Specify
the
operation
mode
and
the
operation
direction
using
the
PRMD
register
(operation
mode).
Since
the
ORG
signal
input
is
latched
internally,
there
is
no
need
to
keep
the
external
signal
ON.
The
ORG
latch
signal
is
reset
when
stopped.
The
minimum
pulse
width
of
the
ORG
signal
is
80
reference
clock
cycles
(4
μsec)
when
the
input
filter
is
ON.
When
the
input
filter
is
turned
OFF,
the
minimum
pulse
width
is
two
reference
clock
cycle
(0.1
μsec).
(When
CLK
=
19.6608
MHz.)
The
input
logic
of
the
ORG
signal
and
EZ
signal
can
be
changed
using
the
RENV1
register
(environment
setting
1).
The
ORG
terminal
status
can
be
monitored
by
reading
SSTSW
(sub
status).
The
EZ
terminal
status
can
be
monitored
by
reading
the
RSTS
register
(extension
status).
For
details
about
the
zero
return
operation
modes,
see
9-5,
"Zero
position
operation
mode."
ORG
signal
and
EZ
signal
timing
Enabling
the
ORG
and
EZ
signals
<Set
MOD
(bits
0
to
6)
in
RMD>
001
0000:
Zero
return
in
the
positive
direction
001
0010:
Leave
zero
position
in
the
positive
direction
001
0101:
Zero
position
search
in
the
positive
direction
010
0100:
EZ
counting
in
the
positive
direction
001
1000:
Zero
return
in
the
negative
direction
001
1010:
Leave
zero
position
in
the
negative
direction
001
1101:
Zero
position
search
in
the
negative
direction
010
1100:
EZ
count
operation
in
the
negative
direction
Set
the
zero
return
method
<Set
ORM0
to
3
(bits
0
to
3)
in
RENV3>
See
the
RENV3
register
description
[RMD]
(WRITE)
7
0
n
n
n
n
n
n
n
0
[RENV3]
(WRITE)
7
-
-
-
-
n
n
n
n
[RENV1]
(WRITE)
7
n
-
-
-
-
-
-
-
0
Set
the
input
logic
for
the
ORG
signal
<Set
ORGL
(bit
7)
in
RENV1>
0:
Negative
logic
1:
Positive
logic
[SSTSW]
(READ)
15
-
n
-
-
-
-
-
-
0
Read
the
ORG
signal
<SORG
(bit
14)
in
SSTSW>
0:
The
ORG
signal
is
OFF
1:
The
ORG
signal
is
ON
[RENV3]
(WRITE)
7
n
n
n
n
-
-
-
-
8
Set
the
EZ
count
number
<Set
EZD0
to
3
(bits
4
to
7)
in
RENV3>
Set
the
zero
return
completion
condition
and
the
EZ
count
number
for
counting.
Specify
the
value
(the
number
to
count
to
1)
in
EZD0
to
3.
The
setting
range
is
0
to
15.
Specify
the
input
logic
of
the
EZ
signal
<Set
EZL
(bit
23)
in
RENV2>
0:
Falling
edge
1:
Rising
edge
Read
the
EZ
signal
<SEZ
(bit
10)
in
RSTS>
0:
The
EZ
signal
is
OFF
1:
The
EZ
signal
is
ON
0
[RENV2]
(WRITE)
23
n
-
-
-
-
-
-
-
[RSTS]
(READ)
15
-
-
-
-
-
n
-
-
16
[RENV1]
(WRITE)
31
-
-
-
-
-
n
-
-
8
Apply
an
input
filter
to
ORG
<Set
FLTR
(bit
26)
in
RENV1>
1:
Apply
a
filter
to
the
ORG
input
By
applying
a
filter,
signals
with
a
pulse
width
of
4
μsec
or
less
will
be
ignored.
24
ORG
EZ
t
(i)
When
t
2
x
T
CLK
,
counts.
(ii)
When
T
CLK
<
t
<
2
x
T
CLK
,
counting
is
undetermined.
(iii)
When
t
T
CLK
,
do
not
count.
T
CLK
:
Reference
clock
frequency
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