參數(shù)資料
型號(hào)： OMAP5910(DSP)
英文描述： Dual-Core Processor
中文描述： 雙核處理器
文件頁數(shù)： 74/160頁
文件大?。?/td> 1997K
代理商： OMAP5910(DSP)
Functional Overview
62
August 2002 Revised August 2003
SPRS197B
Table 320. System DMA Controller Registers (Continued)
RESET
VALUE
ACCESS
TYPE
ACCESS
WIDTH
DESCRIPTION
REGISTER NAME
BYTE
ADDRESS
FFFE:D89A
FFFE:D8BE
Reserved
FFFE:D8C0
SYS_DMA_CSDP_CH3
Channel 3 Source/Destination Parameters Register
16
RW
0000h
FFFE:D8C2
SYS_DMA_CCR_CH3
Channel 3 Control Register
16
RW
0000h
FFFE:D8C4
SYS_DMA_CICR_CH3
Channel 3 Interrupt Control Register
16
RW
0003h
FFFE:D8C6
SYS_DMA_CSR_CH3
Channel 3 Status Register
16
R
0000h
FFFE:D8C8
SYS_DMA_CSSA_L_CH3
Channel 3 Source Start Address Register LSB
16
RW
undef
FFFE:D8CA
SYS_DMA_CSSA_U_CH3
Channel 3 Source Start Address Register MSB
16
RW
undef
FFFE:D8CC
SYS_DMA_CDSA_L_CH3
Channel 3 Destination Start Address Register LSB
16
RW
undef
FFFE:D8CE
SYS_DMA_CDSA_U_CH3
Channel 3 Destination Start Address Register MSB
16
RW
undef
FFFE:D8D0
SYS_DMA_CEN_CH3
Channel 3 Element Number Register
16
RW
undef
FFFE:D8D2
SYS_DMA_CFN_CH3
Channel 3 Frame Number Register
16
RW
undef
FFFE:D8D4
SYS_DMA_CFI_CH3
Channel 3 Frame Index Register
16
RW
undef
FFFE:D8D6
SYS_DMA_CEI_CH3
Channel 3 Element Index Register
16
RW
undef
FFFE:D8D8
SYS_DMA_CPC_CH3
Channel 3 Progress Counter Register
16
RW
undef
FFFE:D8DA
FFFE:D8FE
Reserved
FFFE:D900
SYS_DMA_CSDP_CH4
Channel 4 Source/Destination Parameters Register
16
RW
0000h
FFFE:D902
SYS_DMA_CCR_CH4
Channel 4 Control Register
16
RW
0000h
FFFE:D904
SYS_DMA_CICR_CH4
Channel 4 Interrupt Control Register
16
RW
0003h
FFFE:D906
SYS_DMA_CSR_CH4
Channel 4 Status Register
16
R
0000h
FFFE:D908
SYS_DMA_CSSA_L_CH4
Channel 4 Source Start Address Register LSB
16
RW
undef
FFFE:D90A
SYS_DMA_CSSA_U_CH4
Channel 4 Source Start Address Register MSB
16
RW
undef
FFFE:D90C
SYS_DMA_CDSA_L_CH4
Channel 4 Destination Start Address Register LSB
16
RW
undef
FFFE:D90E
SYS_DMA_CDSA_U_CH4
Channel 4 Destination Start Address Register MSB
16
RW
undef
FFFE:D910
SYS_DMA_CEN_CH4
Channel 4 Element Number Register
16
RW
undef
FFFE:D912
SYS_DMA_CFN_CH4
Channel 4 Frame Number Register
16
RW
undef
FFFE:D914
SYS_DMA_CFI_CH4
Channel 4 Frame Index Register
16
RW
undef
FFFE:D916
SYS_DMA_CEI_CH4
Channel 4 Element Index Register
16
RW
undef
FFFE:D918
SYS_DMA_CPC_CH4
Channel 4 Progress Counter Register
16
RW
undef
FFFE:D91A
FFFE:D93E
Reserved
FFFE:D940
SYS_DMA_CSDP_CH5
Channel 5 Source/Destination Parameters Register
16
RW
0000h
FFFE:D942
SYS_DMA_CCR_CH5
Channel 5 Control Register
16
RW
0000h
FFFE:D944
SYS_DMA_CICR_CH5
Channel 5 Interrupt Control Register
16
RW
0003h
FFFE:D946
SYS_DMA_CSR_CH5
Channel 5 Status Register
16
R
0000h
FFFE:D948
SYS_DMA_CSSA_L_CH5
Channel 5 Source Start Address Register LSB
16
RW
undef
FFFE:D94A
SYS_DMA_CSSA_U_CH5
Channel 5 Source Start Address Register MSB
16
RW
undef
FFFE:D94C
SYS_DMA_CDSA_L_CH5
Channel 5 Destination Start Address Register LSB
16
RW
undef
FFFE:D94E
SYS_DMA_CDSA_U_CH5
Channel 5 Destination Start Address Register MSB
16
RW
undef
FFFE:D950
SYS_DMA_CEN_CH5
Channel 5 Element Number Register
16
RW
undef
FFFE:D952
SYS_DMA_CFN_CH5
Channel 5 Frame Number Register
16
RW
undef
FFFE:D954
SYS_DMA_CFI_CH5
Channel 5 Frame Index Register
16
RW
undef
FFFE:D956
SYS_DMA_CEI_CH5
Channel 5 Element Index Register
16
RW
undef
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