參數(shù)資料
型號： OMAP5910(DSP)
英文描述： Dual-Core Processor
中文描述： 雙核處理器
文件頁數(shù)： 24/160頁
文件大?。?/td> 1997K
代理商： OMAP5910(DSP)
Introduction
12
August 2002 Revised August 2003
SPRS197B
Table 23. Terminal Characteristics and Multiplexing (Continued)
SUPPLY
RESET
STATE#
OTHER
BUFFER
STRENGTH
PU/
PD
§
DESELECTED
INPUT STATE
MUX CTRL
SETTING
TYPE
SIGNAL NAME
GDY
BALL
GZG
BALL
H12
E11
LCD.HS
O
NA
NA
4 mA
J, A, G1
0
DVDD1
DVDD1
DVDD1
DVDD1
B15
A11
LCD.AC
O
NA
NA
4 mA
J, A, G1
0
C15
A12
LCD.PCLK
O
NA
NA
4 mA
J, A, G1
0
D15
C16
A17
G13
B17
C17
D16
D17
C18
B19
A20
H13
G14
C19
B21
D18
D12
C13
B12
F11
B13
E12
A13
C14
B14
A15
C15
B15
A16
D15
C16
B16
LCD.P[15:0]
O
NA
NA
4 mA
J, A, G1
0
C20
C21
E18
D19
D20
F18
A17
D16
B17
E15
E16
C17
KB.C[5:0]
O
NA
NA
4 mA
A, J
0
DVDD1
E19
E20
H14
F19
G18
D17
E17
F15
D14
D13
KB.R[4:0]
I
NA
NA
A, J
input
DVDD1
G19
F14
PWRON_RESET
I
NA
NA
B, J
input
DVDD1
DVDD1
DVDD1
DVDD1
G20
F13
MCBSP1.CLKS
I
NA
NA
B, J
input
G21
G15
MCBSP1.CLKX
I/O/Z
NA
NA
4 mA
J, B, G1
Z
H15
F17
MCBSP1.FSX
I/O/Z
reg4[14:12] = 000
0
4 mA
J, B, G1
Z
MCBSP1.DX
O
reg4[14:12] = 001
NA
H18
F16
MCBSP1.DX
O
reg4[17:15] = 000
NA
4 mA
J, B, G1
0
MCBSP1.FSX
I/O/Z
reg4[17:15] = 001
0
DVDD1
H20
G16
MCBSP1.DR
I
NA
NA
PD20
B , J
input
DVDD1
H19
G13
CAM.EXCLK
O
reg4[23:21] = 000
NA
8 mA
J, A, G1
0
ETM.SYNC
O
reg4[23:21] = 001
NA
DVDD1
UWIRE.SDO
O
reg4[23:21] = 010
NA
J15
H15
CAM.LCLK
I
reg4[26:24] = 000
0
8 mA
B, J
input
ETM.CLK
O
reg4[26:24] = 001
NA
DVDD1
UWIRE.SCLK
O
reg4[26:24] = 010
NA
I = Input, O = Output, Z = High-Impedance
’regx’ denotes the terminal multiplexing register that controls the specified terminal where regx = FUNC_MUX_CTRL_x
§PD20 = 20-
μ
A internal pulldown, PD100 = 100-
μ
A pulldown, PU20 = 20-
μ
A internal pullup, PU100 = 100-
μ
A internal pullup
A = Standard LVCMOS input/output
B = Fail-safe LVCMOS input/output
C = USB transceiver input/output
D = I2C input/output buffers
E = Fail-safe LVCMOS input and Standard LVCMOS output
F = analog oscillator terminals
#Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low
|| UART1 signals can be multiplexed to this pin via additional multiplexing in the USB module.
G1 = Terminal may be gated by BFAIL
G2 = Terminal may be gated by GPIO9 and MPUIO3
G3 = Terminal may be gated by BFAIL and PWRON_RESET
H1 = Terminal may be 3-stated by BFAIL input
J = Boundary-scannable terminal
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