參數(shù)資料
型號： OMAP5910(DSP)
英文描述： Dual-Core Processor
中文描述： 雙核處理器
文件頁數(shù)： 39/160頁
文件大?。?/td> 1997K
代理商： OMAP5910(DSP)
Introduction
27
August 2002 Revised August 2003
SPRS197B
Table 24. Signal Description (Continued)
GDY
BALL
SIGNAL
TYPE
DESCRIPTION
GZG
BALL
Universal Asynchronous Receiver/Transmitter Interfaces
UART1.TX
Y14
P13
TX pin implements the TXIR function during SIR mode operation.
O
UART2.TX
V6,
M18
R4,
J13
UART transmit. Transmit data output. TX is present on all UARTs. On UART3, the
UART3.TX
M18,
K18
J13,
J15
UART1.RX
V14
R11
RX pin implements the RXIR function during SIR mode operation.
I
UART2.RX
R9,
L14
M7,
H12
UART receive. Receive data input. RX is present on all UARTs. On UART3, the
UART3.RX
L14,
K19
H12,
G17
UART1.CTS
R14
M10
UART clear-to-send. CTS is present on all UARTs.
I
UART2.CTS
Y5,
L15
N6,
K15
UART3.CTS
R13,
K15
L10,
H17
UART1.RTS
AA15
U12
this pin is SD_MODE.
O
UART2.RTS
W5,
M19
U4,
J14
UART request-to-send. RTS is present on all UARTs. On UART3 in IrDA mode,
UART3.RTS
Y13,
R19
P11,
M17
UART1.DTR
W21,
Y13
P16,
P11
UART data-terminal-ready. DTR is only present on UART1 and UART3.
O
UART3.DTR
W21
P16
UART1.DSR
U18,
R13
P17,
L10
UART data-set-ready. DSR is only present on UART1 and UART3.
I
UART3.DSR
U18
P17
UART2.BCLK
Y4
T4
UART baud clock output. A clock of 16x of the UART2 baud rate is driven onto this
pin. This feature is only implemented on UART2.
O
Inter-Integrated Circuit Master and Slave Interface
I2C.SCL
T18
P15
I2C serial clock. I2C.SCL provides the timing reference for I2C transfers.
I2C serial data. I2C.SDA provides control and data for I2C transfers.
I/O/Z
I2C.SDA
V20
N14
I/O/Z
LED Pulse Generator Interface
LED1
P18
K12
LED Pulse Generator output 1. LED1 produces a static or pulsing output used to
drive an external LED indicator.
O
LED2
T19
N15
LED Pulse Generator output 2. LED2 produces a static or pulsing output used to
drive an external LED indicator.
O
Multichannel Serial Interfaces (MCSIs)
MCSI1.CLK
AA13
U11
in master mode or an external clock may be driven on this signal in slave mode.
I/O/Z
MCSI2.CLK
Y10
T8
MCSI clock. Multichannel Serial Interface clock reference. The clock can be driven
MCSI1.SYNC
V13
T11
MCSI sync. Multichannel Serial Interface frame synchronization signal. The frame
sync can be driven in master mode or an external clock may be driven on this
signal in slave mode. MCSIx.SYNC may be configured as an active-low or
active-high sync.
I/O/Z
MCSI2.SYNC
V9
R7
I = Input, O = Output, Z = High-Impedance
All core voltage supplies should be tied to the same voltage level (within 0.3 V). During system prototyping phases, it may be useful to maintain
a capability for independent measurement of core supply currents to facilitate power optimization experiments.
§See Sections 5.6.1 and 5.6.2 for special VSS considerations with oscillator circuits.
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