參數(shù)資料
型號： OMAP5910(DSP)
英文描述： Dual-Core Processor
中文描述： 雙核處理器
文件頁數(shù)： 29/160頁
文件大?。?/td> 1997K
代理商： OMAP5910(DSP)
Introduction
17
August 2002 Revised August 2003
SPRS197B
Table 23. Terminal Characteristics and Multiplexing (Continued)
SUPPLY
RESET
STATE#
OTHER
BUFFER
STRENGTH
PU/
PD
§
DESELECTED
INPUT STATE
MUX CTRL
SETTING
TYPE
SIGNAL NAME
GDY
BALL
GZG
BALL
W12
T10
OSC32K_IN
NA
NA
F
NA
NA
R12
T9
OSC32K_OUT
NA
NA
F
NA
NA
W11
R9
MMC.DAT3
I/O/Z
regD[14:12] = 000
1
PU20
4 mA
J, B, G1
input
Reserved
NA
regD[14:12] = 001
NA
DVDD1
MPUIO6
I/O/Z
regD[14:12] = 010
NA
PU20
V11
U10
MMC.CLK
O
NA
NA
4 mA
J, A, G1
0
DVDD1
DVDD1
R11
U9
MMC.DAT0/SPI.DI
I/O/Z
NA
NA
PU20
4 mA
J, B, G1
input
W10
R8
MMC.DAT2
I/O/Z
regA[20:18] = 000
1
PU20
4 mA
J, B, G1
input
pin forced to hi-z
Z
regA[20:18] = 001
NA
DVDD1
MPUIO11
I/O/Z
regA[20:18] = 010
NA
PU20
V10
M9
MMC.DAT1
I/O/Z
regA[26:24] = 000
1
PU20
4 mA
J, B, G1
input
Reserved
NA
regA[26:24] = 001
NA
DVDD1
MPUIO7
I/O/Z
regA[26:24] = 010
NA
PU20
P11
U8
MMC.CMD/SPI.DO
I/O/Z
NA
NA
PU10
0
4 mA
J, B, G1
input
DVDD1
Y10
T8
MCSI2.CLK
I/O/Z
regB[5:3] = 000
0
PD20
4 mA
J, E
input
USB2.SUSP
O
regB[5:3] = 001
NA
DVDD3
AA9
P8
MCSI2.DIN
I
regB[8:6] = 000
NA
PD20
J, B
input
USB2.VP
I
regB[8:6] = 001
0
PD20
DVDD3
W9
T7
MCSI2.DOUT
O
regB[11:9] = 000
NA
4 mA
J, A, G2
0
USB2.TXEN
O
regB[11:9] = 001
NA
DVDD3
V9
R7
MCSI2.SYNC
I/O/Z
regB[14:12] = 000
0
PD20
4 mA
J, E
input
GPIO7
I/O/Z
regB[14:12] = 001
NA
PD20
DVDD3
Y9
U7
MCLK
O
NA
NA
4 mA
J, A, G1
0
DVDD3
R10
N8
MCLKREQ
I
regB[20:18] = 000
0
PD20
4 mA
J, E
input
EXT_MASTER_REQ
O
regB[20:18] = 001
NA
DVDD3
W8
M8
GPIO9
I/O/Z
NA
NA
PD20
4 mA
J, E, G3
input
DVDD3
DVDD3
DVDD3
Y8
U6
GPIO8
I/O/Z
NA
NA
PD20
4 mA
J, E, G3
input
V8
P7
MPUIO3
I/O/Z
NA
NA
PD20
4 mA
J, E, G1
input
P10
R6
MCBSP2.DR
I
regC[2:0] = 000
NA
PD20
4 mA
J, B, G2
input
MCBSP2.DX
O
regC[2:0] = 001
NA
DVDD3
W7
T6
MCBSP2.FSX
I/O/Z
NA
0
PD20
4 mA
J, E, G2
input
DVDD3
V7
T5
MCBSP2.CLKR
I/O/Z
regC[8:6] = 000
0
4 mA
J, E
Z
GPIO11
I/O/Z
regC[8:6] = 001
NA
PD20
DVDD3
Y6
U5
MCBSP2.CLKX
I/O/Z
NA
NA
PD20
4 mA
J, E, G2
input
DVDD3
W6
P6
MCBSP2.FSR
I/O/Z
regC[14:12] = 000
0
4 mA
J, E
Z
GPIO12
I/O/Z
regC[14:12] = 001
NA
PD20
DVDD3
I = Input, O = Output, Z = High-Impedance
’regx’ denotes the terminal multiplexing register that controls the specified terminal where regx = FUNC_MUX_CTRL_x
§PD20 = 20-
μ
A internal pulldown, PD100 = 100-
μ
A pulldown, PU20 = 20-
μ
A internal pullup, PU100 = 100-
μ
A internal pullup
A = Standard LVCMOS input/output
B = Fail-safe LVCMOS input/output
C = USB transceiver input/output
D = I2C input/output buffers
E = Fail-safe LVCMOS input and Standard LVCMOS output
F = analog oscillator terminals
#Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low
|| UART1 signals can be multiplexed to this pin via additional multiplexing in the USB module.
G1 = Terminal may be gated by BFAIL
G2 = Terminal may be gated by GPIO9 and MPUIO3
G3 = Terminal may be gated by BFAIL and PWRON_RESET
H1 = Terminal may be 3-stated by BFAIL input
J = Boundary-scannable terminal
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